am53c94 Advanced Micro Devices, am53c94 Datasheet
am53c94
Related parts for am53c94
am53c94 Summary of contents
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... Supports group 2 and 5 command recognition as per the SCSI-2 specification Advanced CMOS process for low power consumption Am53C94 available in 84-pin PLCC package Am53C96 available in 100-pin PQFP package The patented GLITCH EATER Circuitry in the High Per- formance SCSI Controller detects signal changes that are less than or equal and filters them out ...
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... GLITCH EATER Circuit SYSTEM BLOCK DIAGRAM CPU DMA Memory >15 ns Valid Signal Glitches Glitches pass through as valid signals Glitches Filtered Valid Signal Passes Addr Data Am53C94/96 16 DMA 16 16 Am53C94/Am53C96 <15 ns 16506C-1 9 SCSI Data 9 SCSI Control 16506C-2 ...
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... DMA 15–0 DACK DREQ Address Bus 8-Bit Data Bus DMA Controller Bus Mode Address Bus Data Bus 8 16 DMA Controller Bus Mode 1 Am53C94/Am53C96 AMD Host Bus Processor Controller 16506C-3 Host Bus Processor Controller 16506C-4 3 ...
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... Data Bus AS0 BHE DMARD DMAWR DREQ DACK Bus Mode Address Bus A 3–0 8-Bit Data Bus AD 7–0 16-Bit Data Bus DMA 15–0 DMAWR DREQ DACK Bus Mode 3 Am53C94/Am53C96 Host Processor DMA Controller 16506C-5 Host Processor DMA Controller 16506C-6 ...
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... DFMODE CLK 8 RESET FIFO (including parity) Parity Logic Register Main Bank Sequencer SCSI Sequencer Am53C94/Am53C96 AMD SCSI Bus 9 Data + Parity (Single Ended) SCSI Bus 9 Data + Parity Direction Control 9 SCSI Control 7 SCSI Control Direction Control ...
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... AD4 AD5 AD6 AD7 DREQ Am53C94 84-Pin PLCC Am53C94/Am53C96 DMAWR 74 DACK 73 72 DREQ 71 AD7 70 AD6 ...
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... Microprocessor 80C286 High-Performance 16-Bit 80286 Microprocessor 1–0 Am53C94/96 7– 1–0 Part Number TM Am386 80188 53C80A 85C80 53C94LV Am53C94/Am53C96 AMD SD 7– SDC 7–0 SDCP MSG C/D I/O ATN BSY SEL RST REQ ACK BSYC SELC ...
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... J = 84-Pin PLCC (PL 084 100-Pin PQFP (PQR100) DEVICE NUMBER/DESCRIPTION Am53C94/Am53C96 High Performance SCSI Conroller Valid Combinations list configurations planned to be supported in volume for this device. Consult the lo- cal AMD sales office to confirm availability of specific valid combinations or to check on newly released combinations. Am53C94/Am53C96 Valid Combinations ...
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... SCSI OUTPUT CONNECTIONS Am53C94 Single Ended SCSI Bus Configuration Am53C94 7–0 P SDC , 7–0 P SEL, BSY, REQ, ACK, RST SELC, BSYC, REQC, ACKC, RSTC MSG, C/D, I/O, ATN Am53C94/Am53C96 AMD 16506C-11 9 ...
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... Am53C96 7–0 P SDC , 7–0 P SEL, BSY, REQ, ACK, RST SELC, BSYC, REQC, ACKC, RSTC MSG, C/D, I/O, ATN DFMODE SD , 7–0 P Am53C96 SDC , 7–0 P SEL, BSY, RST SELC, BSYC, RSTC ATN, ACK ISEL MSG, C/D, I/O, REQ TSEL DFMODE Am53C94/Am53C96 V CC 16506C- 16506C-13 ...
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... SDC 75ALS170 SDC SDC SDC 75ALS170 SDC SDC SDC 75ALS170 Am53C94/Am53C96 AMD – – – – – – – – – ...
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... SEL SDC 4 SDC 5 – BSY + BSY SDC 5 SDC 6 – RST + RST SDC 6 SDC 7 – REQ + REQ SDC P – ACK + ACK SDC P Am53C94/Am53C96 SD 0 – – – – – ...
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... DMA bus is transferring data. When using multiplexed bus, these lines can be used for ad- dress and data. When using non multiplexed bus these lines can be used for the data only. Am53C94/Am53C96 AMD 13 ...
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... Mode (DFMODE inactive) these pins are defined as in- puts for the SCSI data bus. When the device is config- ured in the Differential SCSI Mode (DFMODE active) these pins are defined as bidirectional SCSI data bus. Am53C94/Am53C96 Two buses: 8-bit Host Bus and 16-bit DMA Bus Register Address on A 3–0 ...
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... When the device is configured in the Differential SCSI Mode (DFMODE active) this pin is defined as the direction control for the external differential transceiver. In this mode, a signal high state corresponds to an out- put to the SCSI bus and a low state corresponds to an input from the SCSI bus. Am53C94/Am53C96 AMD 15 ...
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... Write 07 Read 07 Write 08 Read/Write 09 Write 0A Write 0B Read/Write 0C Read/Write 0F Write Am53C94/Am53C96 Register Internal State Register Synchronous Transfer Period Register Current FIFO/Internal State Register Synchronous Offset Register Control Register 1 Clock Factor Register Forced Test Mode Register Control Register 2 Control Register 3 Data Alignment Register ...
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... The Reset command and the Stop DMA command are not queued and are exe- cuted immediately. Reading this register will return the 16506C-017 command currently being executed (or the last com- mand executed if there are no pending commands). Am53C94/Am53C96 AMD Address: 02 Type: Read/Write ...
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... Am53C94/Am53C96 Command Information Transfer Initiator Command Complete Steps Message Accepted Transfer Pad Bytes Set ATN Reset ATN Command Send Message Send Status Send Data Disconnect Steps Terminate Steps Target Command Complete Steps Disconnect ...
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... Group 6 commands will always be treated as vendor unique six byte commands and Group 7 commands will always be treated as vendor unique ten byte commands. The GCV bit is cleared by reading the Interrupt Status Register (INSTREG hard or soft reset. Am53C94/Am53C96 AMD H Type: Read 0 I/O ...
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... Type: Write RES RES RES DID2 DID1 DID0 power-up the state of these bits is undefined. The DID 2:0 bits are not affected by reset. SCSI Am53C94/Am53C96 SCSI Destination ID 2:0 Reserved Reserved Reserved Reserved Reserved 16506C-21 ...
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... INSTREG – Bit 0 – SEL – Selected The SEL bit is set at the end of the selection phase indi- cating that the device has been selected and that the ATN signal was inactive during the selection. Am53C94/Am53C96 AMD Selected Selected with Attention Reselected ...
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... The SOF bit is active Low. ISREG – Bits 2:0 – IS 2:0 – Internal State 2:0 The IS 2:0 bits along with the Interrupt Status Register (INSTREG) indicates the status of the successfully completed intermediate operation. Refer to the Status Decode section for more details. Am53C94/Am53C96 s. – ( (8192 (5)) = 122 –3 ...
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... ATN still driven by HPSC Explanation Arbitration steps completed or disconnected or selection time–out Arbitration and selection completed; sequence halted because target failed to assert message out phase; ATN still asserted by HPSC Message out completed; one message byte sent; ATN on Am53C94/Am53C96 AMD 23 ...
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... Received entire CDB Sequence halted during command transfer due to parity error; check FIFO flags Explanation Disconnect steps fully executed; disconnected; bus is free Two message bytes sent; sequence halted because initiator asserted ATN One message byte sent; sequence halted because initiator asserted ATN Am53C94/Am53C96 ...
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... Status and message bytes sent; sequence halted because initiator asserted ATN Status byte sent; sequence halted because initiator asserted ATN Explanation Status and message bytes sent; sequence halted because initiator set ATN Status byte sent; sequence halted because initiator set ATN Command complete steps fully executed Am53C94/Am53C96 AMD 25 ...
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... STP4 STP3 STP2 STP1 STP0 STP4 STP3 Am53C94/Am53C96 H Synchronous Transfer Period 4:0 Reserved Reserved Reserved 16506C-25 Clocks/ STP2 STP1 STP0 Byte ...
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... SOFREG – Bits 7:4 – RES – Reserved SOFREG – Bits 3:0 – SO 3:0 – Synchronous Offset 3:0 The SO 4:0 bits are the binary coded value of the num- ber of bytes that can be sent to (or received from) the SCSI bus without an ACK (or REQ) signal. Am53C94/Am53C96 AMD H Current FIFO 4:0 Internal State 2:0 16506C-26 ...
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... ID on the SCSI bus. The device will arbitrate with this ID and will respond to selection or reselection to this ID. At power-up the state of these bit are undefined. These bits are not affected by hard or soft reset. Am53C94/Am53C96 H Chip ID 2:0 Self Test Enable Parity Error Reporting Enable ...
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... FTMREG – Bit 2 – FHI – Forced High Impedance Mode The FHI bit when set places all the output and bidirec- tional pins into a high impedance state. Am53C94/Am53C96 AMD H Clock Factor 2:0 Reserved Reserved Reserved Reserved Reserved 16506C-29 Input Clock ...
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... When the S2FE bit is re- set the device as a target will request a single message byte initiator, the device will abort the selection sequence if the target does not switch to the command phase after receiving a single message byte. Am53C94/Am53C96 16506C-31 ...
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... DACK signal will toggle for every DMA read. When the MDM bit is reset and the device DMA read or write mode the DACK signal will toggle every time the data is strobed by the DMARD or DMAWR signals. Am53C94/Am53C96 AMD Burst Size 8 Modify DMA Mode Last Byte Transfer Mode ...
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... DMA transfer from the SCSI bus to the host processor is misaligned. Prior to issuing an in- formation transfer command, the host processor must set the Data Alignment Enable (DAE) bit in the CNTLREG2. DALREG – Bits 7:0 – DA 7:0 – Data Alignment 7:0 Am53C94/Am53C96 Maximum Function Synchronous Offset 15 ...
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... General Commands Operation 21 A1 Clear FIFO 22 A2 Reset Device 23 A3 Reset SCSI bus Am53C94/Am53C96 AMD Command Code (Hex.) Non- DMA DMA Mode Mode ...
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... Code 12H) The Message Accepted Command is used to release the ACK signal. This command is normally used to com- Status Register plete a Message In handshake. Upon execution of this command the device generates a service request inter- rupt after REQ is asserted by the target. Am53C94/Am53C96 (CTCREG) is decre- ...
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... Interrupt Status Register (INSTREG) 05H upon command completion. If ATN sig- nal is asserted by the initiator then Successful Operation and Service Request bits are set in the INSTREG, the CMDREG is cleared and Disconnect Steps Command terminates without disconnecting. Am53C94/Am53C96 AMD 35 ...
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... The DMA Stop Command is used by the target to allow the microprocessor to discontinue data transfers due to a lack of activity on the DMA channel. This command is executed from the top of the command queue. If there is a queued command waiting execution, it will be over- written and the Illegal Operation Error (IOE) bit in the Am53C94/Am53C96 ...
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... SCSI bus. When the device wins arbitration, it selects the tar- get device with the ATN signal asserted and transfers the Command Descriptor Block (CDB) and stops after one message byte is sent, but the ATN signal is not Am53C94/Am53C96 AMD 37 ...
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... The Reset SCSI Bus Command is used to assert the RSTC signal for approximately 25 ms. This command causes the device the disconnected state. No interrupt is generated upon command completion. A SCSI reset interrupt is however generated upon com- mand completion if the interrupt is not disabled in the Control Register One (CNTLREG1) 08H. Am53C94/Am53C96 ...
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... OPERATING RANGES – +150 C Commercial Devices . – +125 C Ambient Temperature (T –0 +7.0 V Supply Voltage (V +0. Operating ranges define those limits between which the func- 4000 V pin to pin tionality of the device is guaranteed. Am53C94/Am53C96 AMD ) . . . . . . . + +4. +5. ...
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... DMA 15– DMAP 1–0 and AD 7– < V < V OUT DD DREQ, ISEL – TSEL DREQ, ISEL TSEL 0 V < V < V OUT DD Am53C94/Am53C96 Min Max Unit 4 – 100 +100 2 0 – 0.5 0 300 mV 2 ...
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... A 3-0, CS, RD. WR DMAWR, CLK, BUSMD 1-0, DACK, RESET, and DFMODE All Inputs Hi-Z Outputs AD 7–0, DMA 15–0, DMAP1–0 All Open Drain Outputs All Other Outputs Am53C94/Am53C96 AMD Min Max 2 0 0.5 0.8 SS –10 +10 IL –10 + 16505C-34 3 ...
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... Must be Will be Steady Steady May Will be Change Changing from from May Will be Change Changing from from Don’t Care, Changing, Any Change State Permitted Unknown Does Not Center Apply Line is High- Impedance “Off” State Am53C94/Am53C96 KS000010 ...
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... Reset Pulse Width High PWH Note: There is a one-to-one relationship between every AMD and NCR Parameter (refer to Appendix B Clock Input Test Conditions 5 Reset Input Test Conditions Am53C94/Am53C96 AMD 16505C-36 Min Max Unit 14. 100 ns 54.58 185. ...
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... PD Note: There is a one-to-one relationship between every AMD and NCR Parameter (refer to Appendix B Interrupt Output Test Conditions to RD Set Up Time Delay Delay Am53C94/Am53C96 9 16505C-38 Min Max Unit 100 – t ...
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... Test Conditions Set Up Time Hold Time Set Up Time Hold Time Set Up Time Set Up Time Hold Time Set Up Time Hold Time Am53C94/Am53C96 AMD 16505C-39 Min Max Unit ...
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... Set Up Time Hold Time to CS Set Up Time to Data Valid Delay to RD Set Up Time Hold Time to ALE Set Up Time Set Up Time Set Up Time to ALE Set Up Time Hold Time to CS Hold Time Am53C94/Am53C96 Address Data 16506C-40 Min Max 20 10 ...
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... Test Conditions to DREQ Valid Delay to DACK period to Data Valid Delay to DREQ Valid Delay to DACK period to Data High Impedance to Data Hold Time to DMAWR Set Up Time Set Up Time to DACK Hold Time Hold Time Am53C94/Am53C96 AMD 16506C- 16506C-42 Min Max 38 100 60 ...
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... DMA 15–0 DMAP 1– DMA Write with Byte Control DMA Read with Byte Control Am53C94/Am53C96 16506C- 16506C-53 ...
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... Hold Time to DACK Hold Time to Data High Impedance to Data Hold Time to DREQ Valid Delay to DACK period to DMAWR Set Up Time Set Up Time Set Up Time Hold Time to DACK Hold Time Hold Time Am53C94/Am53C96 AMD Min Max Unit 38 ns 100 ...
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... DMA 15–0 DMAP 1–0 DREQ 82 DACK DMAWR 95 DMA 15–0 DMAP 1– Burst DMA Read without Byte Control 83 101 97 102 100 Burst DMA Write without Byte Control Am53C94/Am53C96 93 94 16506C- 16506C-44 ...
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... Data Valid Delay to DMARD period to DREQ Valid Delay to Data High Impedance to Data Hold Time to DREQ Valid Delay to DMAWR Set Up Time to DMAWR period to DMAWR period Set Up Time to DREQ Valid Delay Hold Time Am53C94/Am53C96 AMD Min Max Unit 45 ns 100 130 ...
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... 103 104 111 109 113 107 110 112 114 108 115 Burst DMA Read with Byte Control 103 104 123 121 125 126 120 122 124 Burst DMA Write with Byte Control Am53C94/Am53C96 116 117 16506C-45 116 117 127 16506C-46 ...
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... Valid Delay to Data High Impedance to Data Hold Time to DREQ Valid Delay to DMAWR Set Up Time Set Up Time to DMAWR period Hold Time to DMAWR period to DREQ Valid Delay Hold Time Set Up Time Am53C94/Am53C96 AMD Min Max Unit 45 ns 100 130 ...
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... 128 130 Asynchronous Initiator Send Test Conditions Set Up Time to Data Delay to ACKC Delay to ACKC Delay 132 Asynchronous Initiator Receive Test Conditions to ACKC Delay to ACKC Delay Am53C94/Am53C96 129 131 16505C-47 Min Max Unit 133 16505C-48 Min Max Unit 43 47 ...
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... 134 136 Asynchronous Target Send Test Conditions Set Up Time to Data Delay to REQC Delay to REQC Delay 138 Asynchronous Target Receive Test Conditions to REQC Delay to REQC Delay Am53C94/Am53C96 AMD 135 137 16505C-49 Min Max 139 16505C-50 Min Max 60 45 Unit ...
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... There is a one-to-one relationship between every AMD and NCR Parameter (refer to Appendix B 142 141 Synchronous Initiator Target Transmit Test Conditions to Data Delay to Data to ACKC or REQC Delay to ACKC or REQC Delay Am53C94/Am53C96 140 142 143 16505C-51 Min Max 15 13 ...
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... APPENDIX A Pin Connection Cross Reference for Am53C94 Pin# AMD 1 DMAP0 DMA8 4 DMA9 5 DMA10 6 DMA11 7 DMA12 8 DMA13 9 DMA14 10 DMA15 11 DMAP1 SD0 12 SD1 13 SD2 14 SD3 15 SD4 16 SD5 17 SD6 18 SD7 19 SDP SDC0 23 SDC1 24 SDC2 25 SDC3 SDC4 28 SDC5 ...
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... SDIP SDO0/ 92 SDO1/ 93 SDO2/ 94 SDO3 SDO4/ 98 SDO5/ 99 SDO6/ 100 Am53C94/Am53C96 AMD NCR SDC SDO7/ 7 SDC SDOP SELC SELO/ BSYC BSYO/ REQC REQO/ ACKC ACKO ...
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... DAN7 t 87 DAN8 t 86 DAN9 t 91 (max) DAN10 t 92 (min) DAN10 t 85 DAN11 t 89 DAN12 t 101 DAN13 t 95 DAN14 Am53C94/Am53C96 AMD NCR AMD Symbol Parameter # t 98 DAN15 t 97 DAN16 t 100 DAN17 t 102 DAN18 t 96 DAN19 t 99 DAN20 t 116 DAB1 t 103 ...
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... For reference only. BSC is an ANSI standard for Basic Space Centering .026 .032 1.150 1.156 1.185 1.195 TOP VIEW Am53C94/Am53C96 .020 MIN .042 .025 R .056 .045 .013 .021 1.000 1.090 REF 1.130 ...
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... PHYSICAL DIMENSIONS* PQR100 Plastic Quad Flatpack Trimmed and Formed (measured in millimeters) PQJ 100 (Plastic Quad Flat Pack; Trimmed and Formed) 0.22 0.38 0.65 REF 2.60 3.00 0.25 MIN (measured in millimeters) 17.10 17.30 13.90 14.10 12.35 REF Pin 1 I.D. TOP VIEW SIDE VIEW Am53C94/Am53C96 AMD 18.85 REF 19.90 20.10 23.00 23.40 3.35 MAX 0.70 15590D 0. 9/6/ ...
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... AMD PHYSICAL DIMENSIONS* PQR100 Molded Carrier Ring Plastic Quad Flatpack (measured in millimeters) 35.50 27.87 22.15 35.90 28.13 22.25 25.15 35.87 31.37 19.80 25.25 36.13 31.63 20.10 .45 Typ .65 Pitch .65 Typ 35.87 36.13 35.50 31.37 35.90 31.63 27.87 25.15 28.13 25.20 BSC 25.25 22.15 13.80 22.25 14. Pin 1 I.D. 80 100 TOP VIEW SIDE VIEW Am53C94/Am53C96 0.22 0.38 .65 NOM 2.00 4.80 1. 6/25/92 SG ...
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... GLITCH EATER is a trademark of Advanced Micro Devices, Inc. AMD and Am386 are registered trademarks of Advanced Micro Devices, Inc. Product names used in this publication are for identification purposes only and may be trademarks of their respective companies Am53C94/Am53C96 AMD 63 ...