cdp1883c Intersil Corporation, cdp1883c Datasheet

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cdp1883c

Manufacturer Part Number
cdp1883c
Description
Cmos 7-bit Latch And Decoder Memory Interfaces
Manufacturer
Intersil Corporation
Datasheet
March 1997
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
http://www.intersil.com or 407-727-9207
Features
• Performs Memory Address Latch and Decoder Func-
• Interfaces Directly with the CDP1800-Series Micropro-
• Allows Decoding for Systems Up to 32K Bytes
Ordering Information
Pinout
CDP1883CE CDP1883E
tions Multiplexed or Non-Multiplexed
cessors
5V
10V
-40
RANGE
TEMP.
|
+85
Copyright
o
C to
o
C
©
PDIP
PACKAGE
Intersil Corporation 1999
CLOCK
MA0
MA1
MA2
MA3
MA4
MA5
MA6
V
CE
SS
E20.3
CDP1883, CDP1883C
10
1
2
3
4
5
6
7
8
9
PKG.
NO.
TOP VIEW
(PDIP)
4-129
Description
The CDP1883 is a CMOS 7-bit memory latch and decoder
circuit intended for use in CDP1800-series microprocessor
systems. It can serve as a direct interface between the multi-
plexed address bus of this system and up to four 8K x 8-bit
memories to implement a 32K-byte memory system. With
four 4K x 8-bit memories, a 16K-byte system can be
decoded.
The device is also compatible with non-multiplexed address
bus microprocessors. By connecting the clock input to V
the latches are in the data-following mode and the decoded
outputs can be used in general-purpose memory-system
applications.
The CDP1833 is compatible with CDP1800-series micropro-
cessors operating at maximum clock frequency.
The CDP1883 and CDP1883C are functionally identical.
They differ in that the CDP1883 has a recommended operat-
ing voltage range of 4V to 10.5V and the C version has a
recommended operating voltage range of 4V to 6.5V.
The CDP1883 and CDP1883C are supplied in 20 lead dual-
in-line plastic packages (E Suffix).
20
19
18
17
16
15
14
13
12
11
V
A8
A9
A10
A11
A12
CS0
CS1
CS2
CS3
and Decoder Memory Interfaces
DD
CDP1883C
CDP1883,
CMOS 7-Bit Latch
File Number
1507.2
DD
,

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cdp1883c Summary of contents

Page 1

... The CDP1883 and CDP1883C are functionally identical. They differ in that the CDP1883 has a recommended operat- ing voltage range 10.5V and the C version has a recommended operating voltage range 6.5V. The CDP1883 and CDP1883C are supplied in 20 lead dual- in-line plastic packages (E Suffix). CDP1883, CDP1883C (PDIP) ...

Page 2

... Voltages Referenced to V Terminal) SS CDP1883 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to +11V CDP1883C -0.5V to +7V Input Voltage Range, All Inputs . . . . . . . . . . . . . -0. Input Current, Any One Input CAUTION: Stresses above those listed in the “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and opera- tion of the device at these or any other conditions above those indicated in the operation section of this specifi ...

Page 3

... Operating current measured at 200kHz for V Functional Diagram MA0 2 MA1 3 MA2 4 MA3 5 MA4 6 MA5 7 MA6 8 CLOCK CDP1883, CDP1883C - + Except as Noted: (Continued CONDITIONS CDP1883 V V (NOTE (V) (V) MIN TYP ...

Page 4

... CS1 CS2 CS3 selects The latched address and decoding functions of the CDP1883 and CDP1883C allow them to operate with 32K byte memory systems. In addition, smaller memory systems can be configured with 4K x 8-bit or smaller memories mix of memory sizes 8-bit ...

Page 5

... However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see web site http://www.intersil.com CDP1883, CDP1883C o o ...

Page 6

... MA0 - MA6 A8 - A12 WAIT CLR A8 - A12 TPA ADDRESS BUS CDP1800 CDM5364 SERIES CPU ROM MRD FIGURE 3. 32K-BYTE ROM SYSTEM USING THE CDP1883 CDP1883, CDP1883C ADDRESS BUS CLK TPA CDP1837C CDP1883 LATCH/ ROM DECODER CS0 CEO CE CS1 CS2 ...

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