npe405h Applied Micro Circuits Corporation (AMCC), npe405h Datasheet
npe405h
Related parts for npe405h
npe405h Summary of contents
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... User accessible performance counters DESCRIPTION Designed specifically to address embedded applica- tions, the NPe405H provides a high-performance, low- power solution that interfaces to a wide range of peripherals by incorporating on-chip power manage requirements ...
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... NPe405H – PowerNP NPe405H Embedded Processor FEATURES .............................................................................................................................................................. 1 DESCRIPTION ........................................................................................................................................................ 1 ORDERING, PVR, AND JTAG INFORMATION ...................................................................................................... 5 AMCC Part Number Key ................................................................................................................................. 5 NPE405H EMBEDDED CONTROLLER FUNCTIONAL BLOCK DIAGRAM ......................................................... 6 ADDRESS MAP SUPPORT .................................................................................................................................... 7 SYSTEM ADDRESS MAP ....................................................................................................................................... 7 DCR ADDRESS MAP .............................................................................................................................................. 8 PLB TO PCI BRIDGE .............................................................................................................................................. 9 SDRAM MEMORY CONTROLLER ....................................................................................................................... 10 EXTERNAL BUS CONTROLLER (EBC) .............................................................................................................. 10 DMA CONTROLLER ...
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... NPe405H – PowerNP NPe405H Embedded Processor TEST CONDITIONS .............................................................................................................................................. 55 CLOCKING SPECIFICATIONS ............................................................................................................................. 56 CLOCKING WAVEFORM ...................................................................................................................................... 56 SPREAD SPECTRUM CLOCKING ....................................................................................................................... 57 PERIPHERAL INTERFACE CLOCK TIMINGS ..................................................................................................... 58 INPUT SETUP AND HOLD WAVEFORM ............................................................................................................. 59 OUTPUT DELAY AND FLOAT TIMING WAVEFORM ......................................................................................... 59 I/O SPECIFICATIONS—ALL ................................................................................................................................ 60 I/O SPECIFICATIONS(A)—133 AND 200 MHZ .................................................................................................... 62 I/O SPECIFICATIONS(A)—266 MHZ .................................................................................................................... 65 INITIALIZATION .................................................................................................................................................... 68 Strapping ...
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... NPe405H – PowerNP NPe405H Embedded Processor Figure 1. NPe405H Embedded Controller Functional Block Diagram ..................................................................... 6 Figure 2. 35mm, 580-Ball E-PBGA Package ......................................................................................................... 14 Figure 3. 5V-Tolerant I/O Input Current ................................................................................................................. 54 Figure 4. Clocking Waveform ................................................................................................................................. 56 Figure 5. Input Setup and Hold Waveform ............................................................................................................. 59 Figure 6. Output Delay and Float Timing Waveform .............................................................................................. 59 Table 1. System Address Map 4GB Total System Memory ..................................................................................... 7 Table 2 ...
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... The PVR (Processor Version Register) is software accessible and contains additional information about the revi- sion level of the part. Refer to the NPe405H User’s Manual for details on the register content. AMCC Part Number Key AMCC Part Number ...
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... The NPe405H is designed using the IBM Microelectronics Blue Logic™ methodology in which major functional blocks are integrated to create an application-specific ASIC product. This approach provides a consistent way to generate complex ASICs using IBM CoreConnect™ Bus Architecture. ...
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... NPe405H – PowerNP NPe405H Embedded Processor ADDRESS MAP SUPPORT The NPe405H incorporates two separate address maps. The first is a fixed processor address map that serves the PowerPC family of processors. This address map defines the possible contents of various address regions which the processor can access. The second address map is for Device Configuration Registers (DCRs). The DCRs are accessed by software running on the NPe405H processor through the use of mtdcr and mfdcr commands ...
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... NPe405H – PowerNP NPe405H Embedded Processor DCR ADDRESS MAP Table 2. DCR Address Map 4KB Device Configuration Register Function DCR address space 1 Reserved Memory controller registers External bus controller registers Reserved PLB registers Performance counters Reserved OPB bridge-out registers Reserved Clock, control and reset ...
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... NPe405H – PowerNP NPe405H Embedded Processor PLB TO PCI BRIDGE The PLB to PCI bridge provides a mechanism for connecting PCI devices to the processor, peripherals, and mem- ory. This interface is PCI Specification rev 2.2 compliant. Features include: • Internal PCI bus arbiter for up to six external devices at PCI bus speeds up to 66MHz. Internal arbiter use is optional and can be disabled for systems which employ an external arbiter. • ...
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... NPe405H – PowerNP NPe405H Embedded Processor SDRAM MEMORY CONTROLLER The NPe405H Memory Controller provides a low latency access path to SDRAM memory. The memory controller supports four logical banks 256MB per bank are supported, for a maximum of 1GB total. Memory access and refresh timing, address and bank sizes, and memory addressing modes are programmable. ...
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... NPe405H – PowerNP NPe405H Embedded Processor DMA CONTROLLER • Supports the following transfers: - Memory-to-memory transfers - Buffered peripheral to memory transfers - Buffered memory to peripheral transfers • Four channels • Scatter/Gather capability for programming multiple DMA operations • 8-, 16-, 32-bit peripheral support (OPB and external bus attached) • ...
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... NPe405H – PowerNP NPe405H Embedded Processor HDLCEX INTERFACE • 32-channel HDLC controller • Two full-duplex Pulse Code Modulation (PCM) Highway ports at speeds up to 4.096 Mbps per port or 8.192 Mbps when using a single port • Supports HDLC protocol as well as a Transparent mode • ...
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... NPe405H – PowerNP NPe405H Embedded Processor 10/100 MBPS ETHERNET MAC • Four units capable of full- and half-duplex, 10 Mbps or 100 Mbps operation • Integrated ZMII Bridge supports use of MII, SMII or RMII connections to external PHYs (PHYs not included on chip) - Reduced Media Independent Interface (RMII) or Serial Media Independent Interface (SMII) for one to four ...
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... NPe405H – PowerNP NPe405H Embedded Processor 35 MM, 580-BALL E-PBGA PACKAGE Figure 2. 35mm, 580-Ball E-PBGA Package Top View Gold gate release corresponds to A01 ball location Bottom View ...
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... NPe405H – PowerNP NPe405H Embedded Processor SIGNAL LISTS The following table lists all the external signals in alphabetical order and shows the ball number on which the signal appears. Multiplexed signals are shown with the default signal (following reset) not in brackets and the alternate signal or signals in brackets. Multiplexed signals appear alphabetically multiple times in the list— ...
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... NPe405H – PowerNP NPe405H Embedded Processor Table 3. Signals Listed Alphabetically (Sheet 2 of 17) Signal Name EMC0MDIO [EMC0Sync]EMC0TxEn[EMC0Tx0En] EMC0TxD0[EMC0Tx0D0][EMC0Tx0D] EMC0TxD1[EMC0Tx0D1][EMC0Tx1D] EMC0TxD2[EMC0Tx1D0][EMC0Tx2D] EMC0TxD3[EMC0Tx1D1][EMC0Tx3D] EMC0TxEn[EMC0Tx0En][EMC0Sync] EMC0TxErr[EMC0Tx1En] [EMC0Tx0En]EMC0TxEn[EMC0Sync] [EMC0Tx1En]EMC0TxErr [EMC1TxEn][EMC1Tx2En]GPIO1_12[HDLCMPTxEn6] [EMC1TxErr][EMC1Tx3En]GPIO1_11[HDLCMPTxData6] [EMC1Tx2En][EMC1TxEn]GPIO1_12[HDLCMPTxEn6] [EMC1Tx3En][EMC1TxErr]GPIO1_11[HDLCMPTxData6] [EMC1TxD0][EMC1Tx2D0]GPIO1_04[HDLCMPRxData4] [EMC1TxD1][EMC1Tx2D1]GPIO1_05[HDLCMPTxClk5] ...
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... NPe405H – PowerNP NPe405H Embedded Processor Table 3. Signals Listed Alphabetically (Sheet 3 of 17) Signal Name GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND ...
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... NPe405H – PowerNP NPe405H Embedded Processor Table 3. Signals Listed Alphabetically (Sheet 4 of 17) Signal Name GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND ...
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... NPe405H – PowerNP NPe405H Embedded Processor Table 3. Signals Listed Alphabetically (Sheet 5 of 17) Signal Name GPIO0_00 GPIO0_01[TS1E] GPIO0_02[TS2E] GPIO0_03[TS1O] GPIO0_04[TS2O] GPIO0_05[TS3] GPIO0_06[TS4] GPIO0_07[TS5] GPIO0_08[TS6] GPIO0_09[DMAReq0] GPIO0_10[DMAReq1] GPIO0_11[DMAReq2] GPIO0_12[DMAReq3][PerCS4] GPIO0_13[DMAAck0] GPIO0_14[DMAAck1] GPIO0_15[DMAAck2] GPIO0_16[DMAAck3][PerCS5] GPIO0_17[IRQ0] GPIO0_18[IRQ1] GPIO0_19[IRQ2] GPIO0_20[IRQ3] GPIO0_21[IRQ4] GPIO0_22[IRQ5] GPIO0_23[IRQ6][PerCS6] ...
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... NPe405H – PowerNP NPe405H Embedded Processor Table 3. Signals Listed Alphabetically (Sheet 6 of 17) Signal Name GPIO1_00[HDLCMPTxClk4][PHY1RxD0][PHY1Rx2D0] GPIO1_01[HDLCMPTxData4][PHY1RxD1][PHY1Rx2D1] GPIO1_02[HDLCMPTxEn4][PHY1RxD2][PHY1Rx3D0] GPIO1_03[HDLCMPRxClk4][PHY1RxD3][PHY1Rx3D1] GPIO1_04[HDLCMPRxData4][EMC1TxD0][EMC1Tx2D0] GPIO1_05[HDLCMPTxClk5][EMC1TxD1][EMC1Tx2D1] GPIO1_06[HDLCMPTxData5][EMC1TxD2][EMC1Tx3D0] GPIO1_07[HDLCMPTxEn5][EMC1TxD3][EMC1Tx3D1] GPIO1_08[HDLCMPRxClk5][PHY1RxErr][PHY1Rx2Er] ...
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... NPe405H – PowerNP NPe405H Embedded Processor Table 3. Signals Listed Alphabetically (Sheet 7 of 17) Signal Name HDLCMPRxClk0 HDLCMPRxClk1 HDLCMPRxClk2 HDLCMPRxClk3 [HDLCMPRxClk4]GPIO1_03[PHY1RxD3][PHY1Rx3D1] [HDLCMPRxClk5]GPIO1_08[PHY1RxErr][PHY1Rx2Er] [HDLCMPRxClk6]GPIO1_13[PHY1RxClk] [HDLCMPRxClk7]GPIO1_18] HDLCMPRxData0 HDLCMPRxData1 HDLCMPRxData2 HDLCMPRxData3 [HDLCMPRxData4]GPIO1_04[EMC1TxD0][EMC1Tx2D0] [HDLCMPRxData5]GPIO1_09[PHY1RxDV][PHY1CrS3DV] [HDLCMPRxData6]GPIO1_14[PHY1Col][PHY1Rx3Er] [HDLCMPRxData7]GPIO1_19 HDLCMPTxClk0 HDLCMPTxClk1 HDLCMPTxClk2 HDLCMPTxClk3 [HDLCMPTxClk4]GPIO1_00[PHY1RxD0][PHY1Rx2D0] ...
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... NPe405H – PowerNP NPe405H Embedded Processor Table 3. Signals Listed Alphabetically (Sheet 8 of 17) Signal Name [IRQ0]GPIO0_17 [IRQ1]GPIO0_18 [IRQ2]GPIO0_19 [IRQ3]GPIO0_20 [IRQ4]GPIO0_21 [IRQ5]GPIO0_22 [IRQ6]GPIO0_23[PerCS6] MemAddr00 MemAddr01 MemAddr02 MemAddr03 MemAddr04 MemAddr05 MemAddr06 MemAddr07 MemAddr08 MemAddr09 MemAddr10 MemAddr11 MemAddr12 MemClkOut0 MemClkOut1 22 DS2011 Revision 1.02 – November 16, 2007 ...
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... NPe405H – PowerNP NPe405H Embedded Processor Table 3. Signals Listed Alphabetically (Sheet 9 of 17) Signal Name MemData00 MemData01 MemData02 MemData03 MemData04 MemData05 MemData06 MemData07 MemData08 MemData09 MemData10 MemData11 MemData12 MemData13 MemData14 MemData15 MemData16 MemData17 MemData18 MemData19 MemData20 MemData21 MemData22 MemData23 MemData24 MemData25 MemData26 ...
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... NPe405H – PowerNP NPe405H Embedded Processor Table 3. Signals Listed Alphabetically (Sheet 10 of 17) Signal Name ...
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... NPe405H – PowerNP NPe405H Embedded Processor Table 3. Signals Listed Alphabetically (Sheet 11 of 17) Signal Name AMCC Proprietary Revision 1.02 – November 16, 2007 Ball Interface Group AL05 AL07 AL09 ...
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... NPe405H – PowerNP NPe405H Embedded Processor Table 3. Signals Listed Alphabetically (Sheet 12 of 17) Signal Name PCIAD00 PCIAD01 PCIAD02 PCIAD03 PCIAD04 PCIAD05 PCIAD06 PCIAD07 PCIAD08 PCIAD09 PCIAD10 PCIAD11 PCIAD12 PCIAD13 PCIAD14 PCIAD15 PCIAD16 PCIAD17 PCIAD18 PCIAD19 PCIAD20 PCIAD21 PCIAD22 PCIAD23 PCIAD24 PCIAD25 PCIAD26 ...
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... NPe405H – PowerNP NPe405H Embedded Processor Table 3. Signals Listed Alphabetically (Sheet 13 of 17) Signal Name PCIINT[PerWE] PCIIRDY PCIParity PCIPErr PCIReq0[Gnt] PCIReq1 PCIReq2 PCIReq3 PCIReq4 PCIReq5 PCIReset PCISErr PCIStop PCITRDY PerAddr00 PerAddr01 PerAddr02 PerAddr03 PerAddr04 PerAddr05 PerAddr06 PerAddr07 PerAddr08 PerAddr09 PerAddr10 PerAddr11 PerAddr12 ...
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... NPe405H – PowerNP NPe405H Embedded Processor Table 3. Signals Listed Alphabetically (Sheet 14 of 17) Signal Name PerBLast PerClk PerCS0 [PerCS1]GPIO0_28 [PerCS2]GPIO0_29 [PerCS3]GPIO0_30 [PerCS4]GPIO0_12[DMAReq3] [PerCS5]GPIO0_16[DMAAck3] [PerCS6]GPIO0_23[IRQ6] [PerCS7]GPIO0_27[EOT3/TC3] PerData00 PerData01 PerData02 PerData03 PerData04 PerData05 PerData06 PerData07 PerData08 PerData09 PerData10 PerData11 PerData12 PerData13 PerData14 PerData15 PerData16 ...
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... NPe405H – PowerNP NPe405H Embedded Processor Table 3. Signals Listed Alphabetically (Sheet 15 of 17) Signal Name PerPar0 PerPar1 PerPar2 PerPar3 PerR/W PerReady PerWBE0 PerWBE1 PerWBE2 PerWBE3 [PerWE]PCIINT PHY0Col[PHY0Rx1Er] PHY0CrS[PHY0CrS0DV] [PHY0CrS0DV]PHY0CrS [PHY0CrS1DV]PHY0RxDV [PHY0RefClk]PHY0TxClk PHY0RxClk PHY0RxD0[PHY0Rx0D0][PHY0Rx0D] PHY0RxD1[PHY0Rx0D1][PHY0Rx1D] PHY0RxD2[PHY0Rx1D0][PHY0Rx2D] PHY0RxD3[PHY0Rx1D1][PHY0Rx3D] PHY0RxDV[PHY0CrS1DV] PHY0RxErr[PHY0Rx0Er] ...
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... NPe405H – PowerNP NPe405H Embedded Processor Table 3. Signals Listed Alphabetically (Sheet 16 of 17) Signal Name TCK [TC0/EOT0]GPIO0_24 [TC1/EOT1]GPIO0_25 [TC2/EOT2]GPIO0_26 [TC3/EOT3]GPIO0_27 TDI TDO TestEn TmrClk TMS [TrcClk]GPIO0_31 TRST [TS1E]GPIO0_01 [TS2E]GPIO0_02 [TS1O]GPIO0_03 [TS2O]GPIO0_04 [TS3]GPIO0_05 [TS4]GPIO0_06 [TS5]GPIO0_07 [TS6]GPIO0_08 [UART0_CTS]GPIO1_26 [UART0_DCD]GPIO1_28 [UART0_DSR]GPIO1_27 [UART0_DTR]GPIO1_31 [UART0_RI]GPIO1_29 [UART0_RTS]GPIO1_30 UART0_Rx ...
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... NPe405H – PowerNP NPe405H Embedded Processor Table 3. Signals Listed Alphabetically (Sheet 17 of 17) Signal Name AMCC Proprietary Revision 1.02 – November 16, 2007 ...
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... NPe405H – PowerNP NPe405H Embedded Processor SIGNALS LISTED BY BALL ASSIGNMENT Table 4. Signals Listed by Ball Assignment (Sheet Signal names followed by an asterisk (*) are multiplexed. Look up the name shown in “Signals Listed Alphabetically” on page 15 for an indication of all signals on the pin. Ball Signal Name ...
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... NPe405H – PowerNP NPe405H Embedded Processor Table 4. Signals Listed by Ball Assignment (Sheet Signal names followed by an asterisk (*) are multiplexed. Look up the name shown in “Signals Listed Alphabetically” on page 15 for an indication of all signals on the pin. Ball Signal Name Ball E01 PCIAD06 ...
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... NPe405H – PowerNP NPe405H Embedded Processor Table 4. Signals Listed by Ball Assignment (Sheet Signal names followed by an asterisk (*) are multiplexed. Look up the name shown in “Signals Listed Alphabetically” on page 15 for an indication of all signals on the pin. Ball Signal Name Ball J01 PerErr ...
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... NPe405H – PowerNP NPe405H Embedded Processor Table 4. Signals Listed by Ball Assignment (Sheet Signal names followed by an asterisk (*) are multiplexed. Look up the name shown in “Signals Listed Alphabetically” on page 15 for an indication of all signals on the pin. Ball Signal Name Ball N01 PerAddr31 ...
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... NPe405H – PowerNP NPe405H Embedded Processor Table 4. Signals Listed by Ball Assignment (Sheet Signal names followed by an asterisk (*) are multiplexed. Look up the name shown in “Signals Listed Alphabetically” on page 15 for an indication of all signals on the pin. Ball Signal Name Ball U01 PerAddr21 ...
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... NPe405H – PowerNP NPe405H Embedded Processor Table 4. Signals Listed by Ball Assignment (Sheet Signal names followed by an asterisk (*) are multiplexed. Look up the name shown in “Signals Listed Alphabetically” on page 15 for an indication of all signals on the pin. Ball Signal Name Ball AA01 PerAddr12 ...
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... NPe405H – PowerNP NPe405H Embedded Processor Table 4. Signals Listed by Ball Assignment (Sheet Signal names followed by an asterisk (*) are multiplexed. Look up the name shown in “Signals Listed Alphabetically” on page 15 for an indication of all signals on the pin. Ball Signal Name Ball AE01 GND ...
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... NPe405H – PowerNP NPe405H Embedded Processor Table 4. Signals Listed by Ball Assignment (Sheet Signal names followed by an asterisk (*) are multiplexed. Look up the name shown in “Signals Listed Alphabetically” on page 15 for an indication of all signals on the pin. Ball Signal Name Ball AJ01 GND ...
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... NPe405H – PowerNP NPe405H Embedded Processor Table 4. Signals Listed by Ball Assignment (Sheet Signal names followed by an asterisk (*) are multiplexed. Look up the name shown in “Signals Listed Alphabetically” on page 15 for an indication of all signals on the pin. Ball Signal Name Ball AN01 GND ...
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... NPe405H has control of the external bus. However, when an external master gains ownership of the external bus, these same pins are used as inputs which are driven by the external master and received by the EBC in the NPe405H. In this example, the pins are also bidirectional, serving as both inputs and outputs. Initialization Strapping One group of pins is used as strapped inputs during system reset. These pins function as strapped inputs only dur- ing reset and are used for other functions during normal operation (see “ ...
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... NPe405H. Unused I/Os Strapping of some pins may be necessary when they are unused. Although the NPe405H requires only the pull-up and pull-down terminations as specified in the “Signal Functional Description” on page 43, good design practice is to terminate all unused inputs or to configure I/Os such that they always drive. If unused, the peripheral, SDRAM, and PCI buses should be configured and terminated as follows: • ...
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... NPe405H – PowerNP NPe405H Embedded Processor SIGNAL FUNCTIONAL DESCRIPTION Table 6. Signal Functional Description (Sheet Notes: 1. Receiver input has hysteresis. 2. Must pull up. See “Pull-up and Pull-down Resistors” on page 42 for recommended termination values. 3. Must pull down. See “Pull-up and Pull-down Resistors” on page 42 for recommended termination values. ...
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... NPe405H – PowerNP NPe405H Embedded Processor Table 6. Signal Functional Description (Sheet Notes: 1. Receiver input has hysteresis. 2. Must pull up. See “Pull-up and Pull-down Resistors” on page 42 for recommended termination values. 3. Must pull down. See “Pull-up and Pull-down Resistors” on page 42 for recommended termination values. ...
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... NPe405H – PowerNP NPe405H Embedded Processor Table 6. Signal Functional Description (Sheet Notes: 1. Receiver input has hysteresis. 2. Must pull up. See “Pull-up and Pull-down Resistors” on page 42 for recommended termination values. 3. Must pull down. See “Pull-up and Pull-down Resistors” on page 42 for recommended termination values. ...
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... NPe405H – PowerNP NPe405H Embedded Processor Table 6. Signal Functional Description (Sheet Notes: 1. Receiver input has hysteresis. 2. Must pull up. See “Pull-up and Pull-down Resistors” on page 42 for recommended termination values. 3. Must pull down. See “Pull-up and Pull-down Resistors” on page 42 for recommended termination values. ...
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... Peripheral output enable. Used by either the external bus controller or the DMA controller depending upon the type of PerOE transfer involved. When the NPe405H is the bus master, it enables the peripherals to drive the bus. Peripheral read/write. Used when not in external master mode by either the external bus controller or DMA controller depending upon the type of transfer involved ...
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... NPe405H – PowerNP NPe405H Embedded Processor Table 6. Signal Functional Description (Sheet Notes: 1. Receiver input has hysteresis. 2. Must pull up. See “Pull-up and Pull-down Resistors” on page 42 for recommended termination values. 3. Must pull down. See “Pull-up and Pull-down Resistors” on page 42 for recommended termination values. ...
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... Hold Primary. Used by an external master to indicate the HoldPri priority of a given transfer (0 = high low). Bus Request. Used when the NPe405H needs to regain BusReq control of peripheral interface from an external Master. Internal Peripheral Interface Serial Clock used to provide an alternative clock to the internally generated serial clock ...
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... NPe405H – PowerNP NPe405H Embedded Processor Table 6. Signal Functional Description (Sheet Notes: 1. Receiver input has hysteresis. 2. Must pull up. See “Pull-up and Pull-down Resistors” on page 42 for recommended termination values. 3. Must pull down. See “Pull-up and Pull-down Resistors” on page 42 for recommended termination values. ...
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... NPe405H – PowerNP NPe405H Embedded Processor Table 6. Signal Functional Description (Sheet Notes: 1. Receiver input has hysteresis. 2. Must pull up. See “Pull-up and Pull-down Resistors” on page 42 for recommended termination values. 3. Must pull down. See “Pull-up and Pull-down Resistors” on page 42 for recommended termination values. ...
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... L1 C1 PACKAGE THERMAL SPECIFICATIONS Table 8. Package Thermal Specifications The NPe405H is designed to operate within a case temperature range of -40°C to 85°C. Thermal resistance values for the E- PBGA packages in a convection environment are as follows: Package—Thermal Resistance 35mm, 580-balls—Junction-to-Case 35mm, 580-balls—Case-to-Ambient Notes: 1 ...
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... NPe405H – PowerNP NPe405H Embedded Processor RECOMMENDED DC OPERATING CONDITIONS Table 9. Recommended DC Operating Conditions Device operation beyond the conditions specified is not recommended. Extended operation beyond the recommended conditions can affect device reliability. Notes: 1. PCI drivers meet PCI specifications. Parameter Symbol Logic Supply Voltage ...
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... NPe405H – PowerNP NPe405H Embedded Processor 5 V-TOLERANT I/O INPUT CURRENT Figure 3. 5V-Tolerant I/O Input Current 100 0 -100 -200 -300 -400 -500 -600 -700 0.0 INPUT CAPACITANCE Table 10. Input Capacitance Parameter 3.3V LVTTL I/O) 5V tolerant LVTTL I/O PCI I/O RX only pins 54 DS2011 1.0 2.0 3.0 Input Voltage (V) Symbol C IN1 C IN2 C IN3 C IN4 Revision 1.02 – ...
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... NPe405H – PowerNP NPe405H Embedded Processor DC ELECTRICAL CHARACTERISTICS Table 11. DC Electrical Characteristics Parameter Active Operating Current for V @ 133MHz DD Active Operating Current for V @ 200MHz DD Active Operating Current for V @ 266MHz DD Active Operating Current for OV @ 133MHz DD Active Operating Current for OV @ 200MHz DD Active Operating Current for OV ...
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... NPe405H – PowerNP NPe405H Embedded Processor CLOCKING SPECIFICATIONS Table 12. Clocking Specifications Symbol SysClk Input F SysClk clock input frequency C T SysClk clock period C T Clock edge stability (phase jitter, cycle to cycle Clock input high time CH T Clock input low time CL Note: Input slew rate > ...
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... The PCI clock specification for 66MHz allows a maximum frequency deviation of − modulation between 30kHz and 33kHz. PCI asynchronous mode is unaffected. Caution the system designer to ensure that any SSCG used with the NPe405H meets the above requirements and does not adversely affect other aspects of the system. ...
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... OPB clock. The maximum OPB clock frequency is 33.33 MHz for 133MHz parts, 50 MHz for 200MHz parts, and 66.66MHz for 266MHz parts. OPB 2. In asynchronous PCI mode the minimum PCIClk frequency is 1/8 the PLB Clock. Refer to the NPe405H User’s Manual for more information. 58 DS2011 Revision 1.02 – ...
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... NPe405H – PowerNP NPe405H Embedded Processor INPUT SETUP AND HOLD WAVEFORM Figure 5. Input Setup and Hold Waveform Clock Inputs OUTPUT DELAY AND FLOAT TIMING WAVEFORM Figure 6. Output Delay and Float Timing Waveform Clock T max OV T min Outputs OH High (Drive) Float (High-Z) ...
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... NPe405H – PowerNP NPe405H Embedded Processor I/O SPECIFICATIONS—ALL Table 14. I/O Specifications—All (Sheet Notes: 1. PCI timings are for asynchronous operation up to 66MHz. PCI output hold time requirement is 1ns for 66MHz and 2ns for 33MHz. Input (ns) Signal Setup Time (T IS min) PCI Interface PCIAD00:31 3 ...
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... NPe405H – PowerNP NPe405H Embedded Processor Table 14. I/O Specifications—All (Sheet Notes: 1. PCI timings are for asynchronous operation up to 66MHz. PCI output hold time requirement is 1ns for 66MHz and 2ns for 33MHz. Input (ns) Signal Setup Time (T IS min) JTAG Interface TCK ...
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... SDRAM I/O timings are specified relative to a MemClkOut terminated in a lumped 10pF load. 4. SDRAM interface hold times are guaranteed at the NPe405H package pin. System designers must use the NPe405H IBIS model (available from www.amcc.com) to ensure their clock distribution topology minimizes loading and reflections, and that the relative delays on clock wiring do not exceed the delays on other SDRAM signal wiring ...
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... SDRAM I/O timings are specified relative to a MemClkOut terminated in a lumped 10pF load. 4. SDRAM interface hold times are guaranteed at the NPe405H package pin. System designers must use the NPe405H IBIS model (available from www.amcc.com) to ensure their clock distribution topology minimizes loading and reflections, and that the relative delays on clock wiring do not exceed the delays on other SDRAM signal wiring ...
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... SDRAM I/O timings are specified relative to a MemClkOut terminated in a lumped 10pF load. 4. SDRAM interface hold times are guaranteed at the NPe405H package pin. System designers must use the NPe405H IBIS model (available from www.amcc.com) to ensure their clock distribution topology minimizes loading and reflections, and that the relative delays on clock wiring do not exceed the delays on other SDRAM signal wiring ...
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... SDRAM I/O timings are specified relative to a MemClkOut terminated in a lumped 10pF load. 4. SDRAM interface hold times are guaranteed at the NPe405H package pin. System designers must use the NPe405H IBIS model (available from www.amcc.com) to ensure their clock distribution topology minimizes loading and reflections, and that the relative delays on clock wiring do not exceed the delays on other SDRAM signal wiring ...
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... SDRAM I/O timings are specified relative to a MemClkOut terminated in a lumped 10pF load. 4. SDRAM interface hold times are guaranteed at the NPe405H package pin. System designers must use the NPe405H IBIS model (available from www.amcc.com) to ensure their clock distribution topology minimizes loading and reflections, and that the relative delays on clock wiring do not exceed the delays on other SDRAM signal wiring ...
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... SDRAM I/O timings are specified relative to a MemClkOut terminated in a lumped 10pF load. 4. SDRAM interface hold times are guaranteed at the NPe405H package pin. System designers must use the NPe405H IBIS model (available from www.amcc.com) to ensure their clock distribution topology minimizes loading and reflections, and that the relative delays on clock wiring do not exceed the delays on other SDRAM signal wiring ...
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... EEPROM connected to the IIC port. The association of bits in the EEPROM with the configuration values and their default values are covered in detail in the PowerNP NPe405H Network Processor User’s Manual. Caution: If SEPROMPresent is strapped to 1, and the EEPROM is not connected or is defective, the NPe405H will not boot up. ...
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... NPe405H – PowerNP NPe405H Embedded Processor DOCUMENT REVISION HISTORY Revision Date 1.02 11/16/07 Page 5, Updated Ordering, PVR, and JTAG Information Table, also included update to footnote. Page 5, Updated AMCC Part Number Key Block. 1.01 04/18/07 Updated SDRAM and MDIO timing in Tables 15 and 16. 1.00 07/29/04 Initial Release AMCC Proprietary Revision 1.02 – ...
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... NPe405H – PowerNP NPe405H Embedded Processor Main Phone: (858) 450-9333 — Technical Support Phone: (858) 535-6517 — (800) 840-6055 http://www.amcc.com (support@amcc.com) AMCC reserves the right to make changes to its products, its datasheets, or related documentation, without notice and war- rants its products solely pursuant to its terms and conditions of sale, only to substantially comply with the latest available datasheet. Please consult AMCC’ ...