54abt377w-qml National Semiconductor Corporation, 54abt377w-qml Datasheet

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54abt377w-qml

Manufacturer Part Number
54abt377w-qml
Description
Octal D-type Flip-flop With Clock Enable
Manufacturer
National Semiconductor Corporation
Datasheet
© 1998 National Semiconductor Corporation
54ABT377
Octal D-Type Flip-Flop with Clock Enable
General Description
The ’ABT377 has eight edge-triggered, D-type flip-flops with
individual D inputs and Q outputs. The common buffered
Clock (CP) input loads all flip-flops simultaneously, when the
Clock Enable (CE) is LOW.
The register is fully edge-triggered. The state of each D in-
put, one setup time before the LOW-to-HIGH clock transi-
tion, is transferred to the corresponding flip-flop’s Q output.
The CE input must be stable only one setup time prior to the
LOW-to-HIGH clock transition for predictable operation.
Features
n Clock enable for address and data synchronization
Ordering Code:
Connection Diagram
TRI-STATE
54ABT377J-QML
54ABT377W-QML
54ABT377E-QML
applications
®
is a registered trademark of National Semiconductor Corporation.
Military
Pin Assignment for
DIP and Cerpack
DS100216
DS100216-1
J20A
W20A
E20A
Package
Number
20-Lead Ceramic Dual-In-Line
20-Lead Cerpack
20-Lead Ceramic Leadless Chip Carrier, Type C
n Eight edge-triggered D flip-flops
n Buffered common clock
n See ’ABT273 for master reset version
n See ’ABT373 for transparent latch version
n See ’ABT374 for TRI-STATE
n Output sink capability of 48 mA, source capability of
n Guaranteed latchup protection
n High impedance glitch free bus loading during entire
n Non-destructive hot insertion capability
n Disable time less than enable time to avoid bus
n Standard Microcircuit Drawing (SMD) 5962-9314801
Names
D
CE
CP
Q
24 mA
power up and power down cycle
contention
Pin
0
0
–D
–Q
7
7
Data Inputs
Clock Enable (Active LOW)
Clock Pulse Input
Data Outputs
Pin Assignment for LCC
Package Description
Description
®
version
DS100216-11
www.national.com
July 1998

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54abt377w-qml Summary of contents

Page 1

... The CE input must be stable only one setup time prior to the LOW-to-HIGH clock transition for predictable operation. Features n Clock enable for address and data synchronization applications Ordering Code: Military 54ABT377J-QML J20A 54ABT377W-QML W20A 54ABT377E-QML E20A Connection Diagram Pin Assignment for DIP and Cerpack DS100216-1 TRI-STATE ® ...

Page 2

Truth Table Operating Mode Load “1” Load “0” Hold (Do Nothing HIGH Voltage Level h = HIGH Voltage Level one setup time prior to the LOW-to-HIGH Clock Transition L = LOW Voltage Level I = LOW Voltage Level ...

Page 3

Absolute Maximum Ratings Storage Temperature Ambient Temperature under Bias Junction Temperature under Bias Ceramic V Pin Potential to CC Ground Pin Input Voltage (Note 2) Input Current (Note 2) Voltage Applied to Any Output in the Disabled or Power-Off State ...

Page 4

AC Electrical Characteristics Symbol Parameter f Max Clock max Frequency t Propagation Delay PLH PHL n AC Operating Requirements Symbol Parameter t (H) Setup Time, HIGH s t (L) or LOW ...

Page 5

AC Loading DS100216-4 *Includes jig and probe capacitance FIGURE 1. Standard AC Test Load = 1.5V FIGURE Input Pulse Requirements Amplitude Rep. Rate 3.0V 1 MHz 500 ns 2.5 ns FIGURE 3. Test Input ...

Page 6

Physical Dimensions inches (millimeters) unless otherwise noted www.national.com 20-Lead Ceramic Chip Carrier NS Package Number E20A 6 ...

Page 7

Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 20-Lead Ceramic Dual-In-Line Package NS Package Number J20A 20-Lead Ceramic Flatpack NS Package Number W20A 7 www.national.com ...

Page 8

LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DE- VICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL SEMI- CONDUCTOR CORPORATION. As used herein: 1. Life support devices ...

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