adsst-21065lks-240 Analog Devices, Inc., adsst-21065lks-240 Datasheet

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adsst-21065lks-240

Manufacturer Part Number
adsst-21065lks-240
Description
High End, Multichannel, 32-bit Floating-point Audio Processor
Manufacturer
Analog Devices, Inc.
Datasheet
a
Melody and SHARC are registered trademarks of Analog Devices, Inc.
DTS, DTS-ES, and DTS 96/24 are registered trademarks of Digital Theater
Dolby and Pro Logic are registered trademarks of Dolby Laboratories
Licensing Corporation.
SRS is a registered trademark and Circle Surround II is a trademark of SRS Labs.
THX is a registered trademark of the THX, Ltd.
*MLP is implemented, not certified.
REV. 0
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices.
Systems, Inc.
FEATURES
Super Harvard Architecture Computer (SHARC)
4 Independent Buses for Dual Data, Instruction, and
32-Bit Fixed-Point Arithmetic; 32-Bit and 40-Bit Floating-
544 Kbits On-Chip SRAM Memory, Integrated I/O
66 MIPS, 198 MFLOPS Peak, 132 MFLOPS Sustained
User-Configurable 544 Kbits On-Chip SRAM Memory
2 External Port, DMA Channels and 8 Serial Port,
Decodes Industry Standard Formats Using a 32-Bit
Dolby
Dolby Pro Logic
Dolby Headphone, Dolby 3/0
DTS
THX
SRS
MPEG AAC, MPEG2 Decode, MPEG 2-Channel Decode
PCM, PCM 96 kHz
HDCD, MLP*
Delay 7.1, 96 kHz
Bass 7.1, 96 kHz, Bass/Treble 2 Channel
ADI Surround: Club, Music, and Stadium
AAC (LC), AAC (LC) 2 Channel, AAC MP
WaveSurround 5.1 Channel to Headphone, Stereo to
Downsampling 96 kHz to 48 kHz (2-Channel)
3-Band Equalizer, 2-Channel
Encoders: AC-3 2-Channel Consumer Encoder
Single Chip DSP-Based Implementation of Digital Audio
I
Interface to External SDRAM
2
S Compatible Ports
I/O Fetch on a Single Cycle
Point Arithmetic
Peripheral I
Transmit Channels
Performance
DMA Channels
Floating Point Implementation for Decoding
Headphone, Channel to Loudspeaker, Stereo to
Loudspeaker
Algorithms
DTS 96/24
®
®
®
5.1, DTS-ES
Labs Circle Surround II
®
Ultra, Select, Ultra2, 5.1, 7.1, EX
Digital AC-3, Dolby Digital EX Processing
®
2
, DTS NEO:6
S Support for 8 Simultaneous Receive and
®
®
, 96 kHz, Dolby Pro Logic II
-Discreet 6.1, DTS Matrix and Matrix 3.0,
TM
, Virtual Loudspeaker
32-Bit Floating-Point Audio Processor
GENERAL DESCRIPTION
The SST-Melody-SHARC family of powerful 32-bit Audio Proces-
sors from Analog Devices provides flexible solutions and delivers
a host of features across high end and high fidelity audio systems
to the AV receiver and DVD markets. It includes multichannel
audio decoders, encoders, and post processors for digital
audio designs using DSP chipsets in home theater systems and
automotive audio receivers.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
Fax: 781/326-8703
Easy Interfaces to Audio Codecs
96 kHz Processing
Supports Customer Specific Post Processing
Automatic Stream Detection and Code Loading
Easy to Use Software Architecture
Optimized Library of Routines
Host Communication Using 16-Bit Parallel Port or SPI Port
Highly Flexible Serial Ports
SRAM Interface for More Delay
Supports IEC60958 For Bit Streams
8-Channel Output Using TDM Codecs
APPLICATIONS
Home Theater AVR Systems
Automotive Audio Receivers
Video Game Consoles
DVD Players
Cable and Satellite Set-Top Boxes
Multimedia Audio/Video Gateways
TRANSMITTER
RECEIVER
DAC
ADC
S/PDIF
S/PDIF
SDRAM
128K
BOOT ROM
1M
FUNCTIONAL BLOCK DIAGRAM
High End, Multichannel,
8
SST-Melody
32,
SERIAL PORT
GPIO
IRQ
ALGORITHMS
SST-Melody-SHARC
DMA CONNECTION
OR DUAL BUFFER
© Analog Devices, Inc., 2002
HOST MICRO
KERNEL
®
-SHARC
(continued on page 11)
www.analog.com
COMMAND
®

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adsst-21065lks-240 Summary of contents

Page 1

... Algorithms Compatible Ports Interface to External SDRAM Melody and SHARC are registered trademarks of Analog Devices, Inc. DTS, DTS-ES, and DTS 96/24 are registered trademarks of Digital Theater Systems, Inc. Dolby and Pro Logic are registered trademarks of Dolby Laboratories Licensing Corporation. SRS is a registered trademark and Circle Surround trademark of SRS Labs. ...

Page 2

SST-Melody-SHARC–SPECIFICATIONS RECOMMENDED OPERATING CONDITIONS Parameter V Supply Voltage DD T Case Operating Temperature CASE V High Level Input Voltage IH V Low Level Input Voltage IL1 V Low Level Input Voltage IL2 NOTES 1 See Environmental Conditions section for information ...

Page 3

... Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Case Temperature Part Number Range ADSST-21065LKS-240 0°C to 85°C ADSST-21065LCS-240 –40°C to +100°C ADSST-21065LKCA-240 0°C to 85°C ADSST-21065LKS-264 0° ...

Page 4

... CAS 43 SDWE 44 45 VDD DQM 46 SDCKE 47 SDA10 48 GND 49 DMAG1 50 DMAG2 51 HBG 52 208-LEAD MQFP PIN CONFIGURATIONS OO ADSST-21065L TOP VIEW (Not to Scale CONNECT –4– 156 VDD 155 GND 154 GND BMS 153 BSEL 152 151 TCK 150 GND 149 TMS 148 ...

Page 5

NC7 NC8 ADDR18 ADDR17 TCK GND ADDR23 ADDR21 RESET TDO BSEL ADDR22 EMU TRST TMS BMS FLAG4 ID1 TDI ID0 FLAG7 FLAG5 FLAG6 VDD DATA29 DATA30 DATA31 VDD DATA26 DATA27 DATA28 VDD DATA23 DATA25 DATA24 VDD ...

Page 6

SST-Melody-SHARC Pin No. Mnemonic Pin No RFS0 54 3 GND 55 4 RCLK0 56 5 DR0A 57 6 DR0B 58 7 TFS0 59 8 TCLK0 GND 62 11 DT0A ...

Page 7

Ball No. Mnemonic Ball No. Mnemonic A1 NC1 B1 DR0A A2 NC2 B2 RFS0 IRQ0 A3 FLAG2 B3 A4 ADDR0 B4 FLAG0 A5 ADDR3 B5 ADDR2 A6 ADDR6 B6 ADDR5 A7 ADDR7 B7 ADDR9 A8 ADDR8 B8 ADDR12 A9 ADDR11 ...

Page 8

SST-Melody-SHARC SST-Melody-SHARC pin definitions are listed below. Inputs identified as synchronous (S) must meet timing requirements with respect to CLKIN (or with respect to TCK for TMS, TDI). Inputs identified as asynchronous (A) can be asserted asynchronously to CLKIN (or ...

Page 9

Mnemonic Type Function HBG Host Bus Grant. Acknowledges an HBR bus request, indicating that the host processor may take control I/O of the external bus. HBG is asserted by the SST-Melody-SHARC until HBR is released multi- processor system, ...

Page 10

SST-Melody-SHARC Mnemonic Type Function TCK I Test Clock (JTAG). Provides an asynchronous clock for JTAG boundary scan. TMS I/S Test Mode Select (JTAG). Used to control the test state machine. TMS has a 20 kΩ internal pull-up resistor. TDI I/S ...

Page 11

GENERAL DESCRIPTION (continued from page 1) With 32-bit audio quality, the SST-Melody-SHARC audio processor auto-detects and decodes audio formats in real-time, enabling end users to enjoy a theater-quality audio experience in their homes. The solutions can be customized to meet ...

Page 12

SST-Melody-SHARC SOFTWARE ARCHITECTURE The audio DSP chipsets from Analog Devices allows designers to make value additions to product features working off the high end base functionality that they are provided with. The software has the following parts: SST-Melody-SHARC • Executive ...

Page 13

Independent, Parallel Computation Units The arithmetic/logic unit (ALU), multiplier, and shifter all perform single-cycle instructions. The three units are arranged in parallel, maximizing computational throughput. Single multifunction instructions execute parallel ALU and multiplier operations. These computation units support IEEE 32-bit ...

Page 14

SST-Melody-SHARC Systems with several SDRAM devices connected in parallel may require buffering to meet overall system timing requirements. The SST-Melody-SHARC supports pipelining of the address and control signals to enable such buffering between itself and mul- tiple SDRAM devices. Host ...

Page 15

POWER DISSIPATION These specifications apply to the internal power portion of V supply current and total supply current. For a complete discussion of the code used to measure power dissipation, see the technical note SHARC Power Dissipation Measurements. Specifications are ...

Page 16

SST-Melody-SHARC OUTPUT DRIVE CURRENT 80 V 3.6V, – 3.3V, + 3.1V, +100 C 0 –20 3.1V, +100 C –40 3.3V, +25 C –60 3.1V, +85 C – –100 –120 0 0.50 1.00 1.50 ...

Page 17

RISE TIME 4.0 3.0 2.0 1 100 120 LOAD CAPACITANCE – pF Figure 8. Typical Rise and Fall Time (0.8 V–2 –1 ...

Page 18

SST-Melody-SHARC The P equation is calculated for each class of pins that can drive: EXT Pin Type No. of Pins Address 11 MS0 1 SDWE 1 Data 32 SDRAM CLK 1 A typical power consumption can now be calculated for ...

Page 19

BSC SQ 1.70 MAX 3.60 3.40 3.20 0.50 0.08 (LEAD 0.25 COPLANARITY) VIEW A ROTATED 90 CCW REV. 0 OUTLINE DIMENSIONS 196-Lead Chip Scale Ball Grid Array [CSPBGA] (BC-196) Dimensions shown in millimeters 1.00 BSC BALL PITCH TOP VIEW ...

Page 20

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