tsc695fl ATMEL Corporation, tsc695fl Datasheet

tsc695fl

Manufacturer Part Number

tsc695fl

Description

Sparc Processor

Manufacturer

ATMEL Corporation

Datasheet

1.TSC695FL.pdf (4 pages)

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Active Errata List

•

Errata History

Errata Description

1. DMA Access Request During Processor LOCK Accesses

2. BUSRDY* and Waitstates on Exchange Memory Area

Product Release

All lot numbers

DMA Access Request During Processor LOCK Accesses

BUSRDY* and Waitstates on Exchange Memory Area

Floating-point Compare Instruction Followed by OR Instruction

The error case appears when the DMAREQ* assertion by the DMA unit and the

LOCK assertion by the processor occur in the same clock cycle. In this case, if no

DMA transfer is performed during the DMA session, the processor only retrieves

control on the bus after the DMA time-out has expired. The DMA time-out can be

disabled by software. If DMA time-out is disabled and the error case is present,

the processor will never retrieve the bus. A reset would be the only way to restart

processor in normal activity.

When the error case condition is fulfilled, on the same clock rising edge,

DMAGNT* assertion by the processor and internal LOCK sampling by the mem-

ory controller are executed. A DMA session is started and at the same time, the

LOCK signal is decoded by the MEC. The memory controller generates an inter-

nal signal that makes the IU enter a ‘hold’ mode. The IU remains in ‘hold’ mode

until internal signals are updated through DMAAS assertion or DMA time-out. The

external LOCK pin is a direct representation of the IU signal whereas internal

LOCK is only effective in the following rising edge of the clock.

Workarounds

Software workaround:

No inactive DMA cycle is performed. At least one DMAAS per DMA cycle.

Hardware workaround:

The DMA unit must decode the LOCK signal so that no DMA request is sent to the

processor while a locked cycle is in progress. Insertion of a one-clock-cycle delay

on assertion of DMAREQ* when LOCK is active is one way to avoid the above

processor behavior.

The error appears during exchange memory accesses that use both programmed

waitstates and BUSRDY*.

An exchange memory access is only terminated if on the rising edge of SYSCLK

that separates the ‘waitstate cycle’ and the ‘end of cycle’ the BUSRDY* signal is

low.

If BUSRDY* is high and the programmed waitstates are elapsed, the processor

remains in a waiting state. It retrieves a nominal behaviour when a bus timeout

occurs.

Workarounds

When ‘n’ waitstates are programmed, generate a ‘n+2’ SYSCLK cycles length

BUSRDY*.

When the programmed waitstates elapse, assert a second pulse of BUSRDY*.

Errata List

1, 2, 3

SPARC

Processor

TSC695

Errata Sheet

4280D–AERO–07/06

Related parts for tsc695fl

tsc695fl Summary of contents

Page 1

Active Errata List • DMA Access Request During Processor LOCK Accesses • BUSRDY* and Waitstates on Exchange Memory Area • Floating-point Compare Instruction Followed by OR Instruction Errata History Product Release All lot numbers Errata Description 1. DMA Access Request ...

Page 2

Floating-Point Compare Single or Double Instruction followed by specific IU Instruction followed by Float- ing-Point Store Double Instruction If a floating-point compare single or double instruction (FCMPS, FCMPES, FCMPD or FCMPED) is immediately followed by one of the OR, ...

Page 3

IUop STD – Case 4: FCMPED %fx,%fy NOP IUop STD Note: If direct control over assembly language is not possible (high-level programming language such as C), checking of the SPARC binary code against any of the four above mentioned faulty ...

Page 4

... Atmel products are not suitable for, and shall not be used in, automotive applications. Atmel’s products are not intended, authorized, or warranted for use as compo- nents in applications intended to support or sustain life. © Atmel Corporation 2006. All rights reserved. Atmel tered trademarks, of Atmel Corporation or its subsidiaries. Other terms and product names may be trademarks of others. Atmel Operations ...

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