w6691 Winbond Electronics Corp America, w6691 Datasheet

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w6691

Manufacturer Part Number
w6691
Description
Isdn S/t Interface Transceiver
Manufacturer
Winbond Electronics Corp America
Datasheet
W6691 Preliminary
ISDN S/T Interface Transceiver
W6691 ISDN S/T Interface Transceiver
Data Sheet
The information described in this document is the exclusive intellectual property of Winbond Electronics
Corp and shall not be reproduced without permission from Winbond.
Winbond is providing this document only for reference purposes for W6691-based system design. Winbond
assumes no responsibility for errors or omissions. All data and specifications are subject to change without
notice.
Publication Release Date: Sep 2001
1
Revision 1.1

Related parts for w6691

w6691 Summary of contents

Page 1

... The information described in this document is the exclusive intellectual property of Winbond Electronics Corp and shall not be reproduced without permission from Winbond. Winbond is providing this document only for reference purposes for W6691-based system design. Winbond assumes no responsibility for errors or omissions. All data and specifications are subject to change without notice ...

Page 2

... GCI Mode Monitor Channel Handling..............................................................................................50 7.7 8-bit Microprocessor Interface ........................................................................................................ 52 8 REGISTER DESRCRIPTIONS.......................................................................................................... 53 8.1 D Channel HDLC Controller Register Address Map......................................................................... 53 8.2 GCI Bus Control Register Address Map ........................................................................................... 54 8.3 Miscellaneous Register Address Map .............................................................................................. 55 8.4 D Channel HDLC Controller Register Memory Map ......................................................................... 55 Preliminary W6691 Publication Release Date: Sep 2001 2 Revision 1.1 ...

Page 3

... MO0C Read/Write Address 23H .....................................73 GCR Read MO1R Read Address 27H ...........................................75 MO1X Read/Write MO1I Read_clear MO1C Read/Write Address 2AH ....................................76 CI1R Read Address 31H ........................................................77 3 Preliminary W6691 H ...............................64 Address 1BH ...................................71 Address 22H .................................73 Address 26H .....................................74 Address 28H.......................75 Address 29H ...............................76 Publication Release Date: Sep 2001 Revision 1.1 ...

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... B1_ADM1 Read/Write Address B1_ADM2 Read/Write Address 5AH .....................................93 B1_ADR1 Read/Write Address 5BH ...........................................93 B1_ADR2 Read/Write Address 5CH ...........................................93 B1_RBCL Read Address 5DH ................................93 B1_RBCH Read Address 5EH ...............................94 B1_IDLE Read/Write Address 5FH .............................................94 4 Preliminary W6691 Address 3CH 83 Address 57H ................91 59H ..................................92 Publication Release Date: Sep 2001 Revision 1.1 ...

Page 5

... AC Timing Test Conditions............................................................................................................. 104 10. ORDERING INFORMATION ........................................................................................................ 104 11. PACKAGE DIMENSIONS ............................................................................................................ 105 LIST OF FIGURES FIG.3.1 W6691 PIN CONFIGURATION - INTEL BUS MODE ............................................................. 10 FIG.3.2 W6691 PIN CONFIGURATION – MOTOROLA BUS MODE .................................................. 12 FIG.5.1 ISDN INTERNET PASSIVE S-CARD WITH TWO POTS CONNECTIONS ........................... 16 FIG.5.2 ISDN PAXB APPLICATION ..................................................................................................... 17 FIG.6.1 W6691 FUNCTIONAL BLOCK DIAGRAM .............................................................................. 18 FIG ...

Page 6

... TABLE 8.5 GCI BUS REGISTER MEMORY MAP ............................................................................... 57 TABLE 8.7 B1 CHANNEL HDLC CONTROLLER REGISTER ADDRESS MAP.................................. 86 TABLE 8.8 B1 CHANNEL HDLC CONTROLLER REGISTER MEMORY MAP ................................... 87 TABLE 8.9 B2 CHANNEL HDLC CONTROLLER REGISTER ADDRESS MAP.................................. 95 TABLE 8.10 B2 CHANNEL HDLC CONTROLLER REGISTER MEMORY MAP ................................. 95 Preliminary W6691 Publication Release Date: Sep 2001 6 Revision 1.1 ...

Page 7

... The first version is edited. Sep 2001 1.1 Content of Revision 1. W6691 Pin Configuration -- Intel Bus mode is modified on page11. 2. W6691 Pin Configuration – Motorola Bus Mode is modified on page 12 3. Pin Description is modified on page 13. 4. The chapter 7.1.2 Interface and Operating Mode description is changed on page 20. ...

Page 8

... W6691 chip internal control. The DPLL circuit is design in chip to generate the DCL and FSC signal for NT2 application. It can eliminate extra DPLL circuit on board. In order to save a lot of crystal on board, W6691 can provide 7.68MHz OSC signal for other chip needs the clock NT2 application. ...

Page 9

... Added reset signal to reset other chip. Loop back function for testing. Layer1 Activate Indication Output can be connected to LED Two of programmable timer 3.3 Volt power supply 3.3 Volt output; Maximum Input is 5.0Volt Advanced CMOS technology 64 pin LQFP or 68 pin PLCC package Preliminary W6691 Publication Release Date: Sep 2001 9 Revision 1.1 ...

Page 10

... PIN CONFIGURATIONS VDD VSS C16.384 MBS PFCK2 PFCK1 PBCK PTXD PRXD VDD VSS DU DD FSC DCL INT# Fig.3.1 W6691 Pin Configuration - Intel Bus Mode ...

Page 11

... FSC 63 DCL INT Preliminary W6691 ...

Page 12

... Fig.3.2 W6691 Pin Configuration – Motorola Bus Mode 12 Preliminary W6691 Publication Release Date: Sep 2001 Revision 1.1 ...

Page 13

... PIN DESCRIPTION TABLE 4.1 W6691 PIN DESCRIPTIONS Note: The suffix "#" indicates an active LOW signal. In Intel or Motorola bus mode, all unspecified pins must be left unconnected. Pin Pin Name Number MBS 52 AD7-0 23, 24, 25, 26, 27, 28, 29, 30 CS# 11 ALE 10 RD# 9 WR# 22 RST# 3 INT# ...

Page 14

... PCM bus receive data input. A maximum of two channels with 64 Kbits/s data rate can be multiplexed on this signal. It needs external pull-up. ISDN Signals and External Crystal I S/T bus receiver input (negative). I S/T bus receiver input (positive). O S/T bus transmitter output (positive). 14 Preliminary W6691 4.096MHz for LT-T/LT-S Publication Release Date: Sep 2001 mode(NT2 Revision 1.1 ...

Page 15

... ACTL1S pin is driven to high level. 1: The ACTL1 output level is programmed by microprocessor (ACTL2 : ACLT1S). Power and Ground I Digital Power Supply (3V 5%). I Analog Power Supply (3V 5%). I Digital Ground. I Analog Ground. 15 Preliminary W6691 clock input. The clock frequency: Publication Release Date: Sep 2001 Revision 1.1 ...

Page 16

... SYSTEM DIAGRAM AND APPLICATIONS NT 4-wire S/T Phone FAX Transfomer Protection Module Circuit PCM POTS CODEC Circuit X2 Fig.5.1 ISDN TA with Two POTS Connections 16 Preliminary W6691 S Interface W6691 Microprocessor Publication Release Date: Sep 2001 Revision 1.1 ...

Page 17

... S interface GCI TE LT-S W6691 W6691 Clock UP Generator Fig.5.2 ISDN PAXB Application 17 Preliminary W6691 7.68MHz GCI T interface LT-T TSI W6691 8KHz(FSC) 512KHz 4.096MHz(DCL) Publication Release Date: Sep 2001 Revision 1.1 ...

Page 18

... BLOCK DIAGRAM The block diagram of W6691 is shown in Figure 6.1 Transceiver 4-wire S/T AMI/BIN Conversion GCI Bus Circuit Crystal/Oscillator DPLL1 and Timing Generator (7.68 MHz) POTS circuit FSCO DCLO C16.384 2B+D 2B+D Slip Line Buffer & 2B+D GCI I/O Control DPLL2 Fig.6.1 W6691 Functional Block Diagram 18 Preliminary W6691 GCI Bus ...

Page 19

... FUNCTIONAL DESCRIPTIONS 7.1.1 Main Block Functions The functional block diagram of W6691 is shown in Fig.6.1. The main function blocks are: - Layer 1 function according to ITU-T I.430 - B channel switching - GCI bus interface - PCM port (x 2) and internal B channel switching - D channel HDLC controller - DPLL 2 circiut generating 4.096 MHz clock for NT2 application ...

Page 20

... The peripheral simple I/O is used to control other peripheral devices such as CODEC, SLIC, DTMF detector, LEDs. 7.1.2 Interface and Operating Modes The W6691 can be configured for the following application: l ISDN terminals --- TE mode (M1=0 & M0=0) l ISDN subscriber line termination --- LT-S mode (M1=1 & M0=0) l ISDN trunk line termination ---LT-T mode (M1=0 & M0= LT-S and LT-T modes are configured by setting mode pins (M1 and M0) ...

Page 21

... N = Bit set to a binary value N Bit within B channel Bit within B channel Bit used for activation S = Bit used for S channel M = Multiframe bit Fig.7.1 Frame structure at S/T interface 21 Preliminary W6691 ...

Page 22

... W6691 TE1 (c) Extended passive bus configuration Fig.7.2 W6691 wiring configuration in TE applications The transmitter and receiver are implemented by differential circuits to increase signal to noise ratio (SNR). The nominal differential line pulse amplitude at 100 1:1 turn ration are needed at transmitter and receiver for voltage level translation and DC isolation. ...

Page 23

... The diode bridge is used for overvoltage protection. 5-10 SX1 GND SX2 resistors (1.8 k VDD 5-10 Fig.7.3 External Transmitter Circuitry 23 Preliminary W6691 +8 limit the peak current in 2:1 100 Publication Release Date: Sep 2001 Revision 1.1 ...

Page 24

... S interface. The power down state is left either by non-INFO 0 signal from S interface or C/I command from microprocessor. 1.8k GND 1.8k Fig.7.4 External Receiver Circuitry 24 Preliminary W6691 2:1 8.2k 100 VDD 8.2k Publication Release Date: Sep 2001 Revision 1.1 ...

Page 25

... OPS1 OPS0 W6691 does not need RC filter on receiver side, therefore zero delay compensation is selected normally. This is also the default setting. The PCM output clocks (PFCK1-2, PBCK) are locked to the S-interface timing with jitter. See the electrical specification. Effect 0 No phase delay compensation ...

Page 26

... F3 Awaiting Deactivation The W6691 enters this state after receiving INFO 0 (in states F5 to F8) for 16ms (64 frames). This time constant prevents spurious effect on S interface. Any non-INFO 0 signal on the S interface causes transition to " ...

Page 27

... This is the normal active state with the layer 1 protocol activated in both directions. From state "F6 Synchronized" , state F7 is reached at most 0.5 ms after reception of INFO 4. From state "F3 Deactivated without clock" with the clocks disabled, state F7 is reached at most 6 ms after the W6691 is directly activated by INFO 4. ...

Page 28

... Signal received, receiver not synchronous 1000 INFO 2 received TI 1010 Analog loopback activated or continuous zeros or single zeros transmitted ATI 1011 Level detected during test function AI8 1100 INFO 4 received, D channel priority Preliminary W6691 Publication Release Date: Sep 2001 Revision 1.1 ...

Page 29

... Note that the command code writtern by the microprocessor in CIX register and indication code written by layer 1 in CIR register are transmitted repeatedly until a new code is written. AI10 1101 INFO 4 received, D channel priority 1111 Layer 1 deactivated, internal clocks are disabled 29 Preliminary W6691 Publication Release Date: Sep 2001 Revision 1.1 ...

Page 30

... Fig.7.5 layer 1 activation/deactivation state diagram - normal mode Fig.7.5 layer 1 activation/deaction state diagram – TE/LT-T normal mode DRC CE ECK ARD AI8/ Preliminary W6691 F3 Deact w/o clk AR8/10 DRC ECK DRC F3 Deact with clk AR8/10 ECK ECK DRC F3 Await. Deact. ...

Page 31

... RST can be issued at any state, while SCP, SCZ and EAL can be issued only F7 one of the commands : ECK, DRC, RST. 3. Continuous pulses at 96 kHz. 4. Isolated pulses at 2 kHz. 5. The INFO 3 is transmitted internally only. Fig.7.6 layer 1 activation/deactivation state diagram – TE/LT-T SPECIAL mode Preliminary W6691 Ana. Loop Init. EAL EAL Ignored 5) i3 Ana ...

Page 32

... This state is requested by DDR (deactivate request). If INFO0 is received during 16ms or an internal timer2 expiration, the layer1 responses DRIU indication for Layer2. G4 Await Deactivated The W6691 stays in this state and waits for DRIU report from layer2. If W6691 receives DRA command from layer2, it enters G1 state. Test Mode Continuous Pulses Continuous alternating 96 KHz pulses are sent. ...

Page 33

... INFO 1 signal detected is responsed to Layer2. AIU 1100 Synchronous receiver DRIU 1111 1. Timer2 expired 2. info 0 received during 25ms after deactivation request command RSTI 0001 Reset state indication TI 0000 33 Preliminary W6691 Info3 and try to re-synchronize Publication Release Date: Sep 2001 Revision 1.1 ...

Page 34

... G2 Pending Act DDR/ARD I0/i1 G3 Activated DDR/ARD i3 pulse ^i3 Lost of Frame DDR/ARD ^i3 G4 pending deact ARD DDR i0/i1/i3 G4 Await deact ARD DDR i0/i3 DRA 34 Preliminary W6691 G1 Deact DDR DRIU i0 ARD or i1 DDR ARIU i2 i3 DDR AIU i4 i3 DDR SSYN i2 DDR AIU i0 i0 during 25ms or T2 expire ...

Page 35

... Remarks AR8 1000 Activation command, set D channel priority to 8 AR10 1001 Activation command, set D channel priority to 10 Abbr. Remarks 1100 Info 4 received, D channel priority 1101 Info 4 received, D channel priority Preliminary W6691 Publication Release Date: Sep 2001 Revision 1.1 ...

Page 36

... Frame Alignment The following sections describe the behavior of W6691 in respect to the CTS-2 conformance test procedures for frame alignment. Please refer to ETSI-TM3 Appendix B1 for detailed descriptions. 7.2.6.1 FAinfA_1fr This test checks if TE does not lose frame alignment on receipt of one bad frame. The pattern for the bad frame is defined as IX_96 kHz ...

Page 37

... This is to test the number k of IX_I4noflag frames necessary for loss of frame alignment. Device W6691 7.2.6.7 Faregain This is to test the number m of good frames necessary for regain of frame alignment. The TE regains frame alignment at m+1 frame. The W6691 achieves synchronization after 5 frames, i.e m=4. Device W6691 Settings Result k =2 ...

Page 38

... S bit is transmitted from NT to TE. The S and Q bit A positions and multiframe structure are shown in Table 7.10. The functions provided by W6691 are: - Multiframe synchronization: Synchronization is achived when the M bit pattern has been correctly received during 20 consecutive frames starting from frame number 1. ...

Page 39

... S3 ZERO ZERO ZERO ZERO ZERO ZERO ZERO ZERO ZERO S4 ZERO ZERO ZERO ZERO ZERO ZERO ZERO ZERO ONE S1 ZERO ZERO 39 Preliminary W6691 TE-to-NT F -bit position A Q1 ZERO ZERO ZERO ZERO Q2 ZERO ZERO ZERO ZERO Q3 ZERO ZERO ZERO ZERO Q4 ZERO ZERO ZERO ZERO ...

Page 40

... S bus timing. This loop function is used for test of PCM and higher layer functions, excluding layer 1. After hardware reset, W6691 will power down if S bus is not connected or if there is no signal on the S bus. In this case, the C/I command ECK must be issued to power up the chip ...

Page 41

... B Channel Switching W6691 provides five kinds of B channel switching function. 1. PCM and GCI bus Switch (SFCTL : PGSWH determines the CODEC interface operated in B channel. 1: PCM bus is selected to operate with CODEC. 0: GCI bus is selected to operate with CODEC. 2. PCM Remote Loop Back (SFCTL : PCRLP) Setting this bit activates the PCM channel remote loopback function ...

Page 42

... Select B1 channel switch between Layer1/GCI and PCM. 10: Select B1 channel switch between PCM and Layer2. 7.4 PCM Port There are two PCM ports in W6691. Data is valid when respective PFCK is HIGH. The frame synchronization clocks (PFCK1-2) are 8 kHz and the bit synchronization clock (PBCK) is 1.536 MHz. 7.5 D Channel HDLC Controller There are two HDLC protocols that are used for ISDN layer 2 functions : LAPD and LAPB ...

Page 43

... P P information ( octets) 1st octet N( P information ( octets) 43 Preliminary W6691 flag (1 octet FCS flag (2 octets) (1 octet) 2nd octet N(R) 1 N(R) 1 FCS flag (2 octets) (1 octet) Publication Release Date: Sep 2001 ...

Page 44

... Note. The LAPD protocol uses the CRC_ITU-T for Frame Check Sequence. The polynominal For address recognition, the W6691 provides four programmable registers for individual SAPI and TEI values, SAP1-2 and TEI1-2, plus two fixed values for group SAPI and TEI, SAPG and TEIG. The SAPG equals 02H(C/R=1) or 00H(C/R=0) which corresponds to SAPI = 0 ...

Page 45

... When a D_RMR or D_RME interrupt is generated, the micro-processor must read out the data from D_RFIFO and issues the Receive Message Acknowledgement command (D_CMDR: RACK bit) to explicitly Preliminary W6691 32 bytes has been received. The Publication Release Date: Sep 2001 45 Revision 1 ...

Page 46

... If the microprocessor fails to respond the D_XFR interrupt within a given time (16 ms), a data underrun condition will occur. The W6691 will automatically reset the transmitter and send inter frame time fill pattern (all 1' channel. The microprocessor is informed about this condition via an XDUN (Transmit Data Underrun) interrupt in D_EXIR register ...

Page 47

... The GCI is a generalization and enhancement of the general purpose, serial interface bus. The channel structure of the GCI mode is depicted below. The timing is compatible with Siemens’s IOM-2 mode. TE Mode Timing TE mode contains three channels. The structure of TE mode is show in Fig7.10. Preliminary W6691 Publication Release Date: Sep 2001 47 Revision 1.1 ...

Page 48

... Kbits/s B channel Monitor channel 16Kbits/s D channel CI0: 48Kbits/s Command / Indication Channel A/E : 16Kbits Monitor channel handshake signaling M1: Monitor channel1 CI1: 48Kbits/s Command / Indication Channel Fig.7.10 GCI TE Mode Channel Structure 48 Preliminary W6691 CI1 A E CH2 Publication Release Date: Sep 2001 Revision 1.1 ...

Page 49

... DCL FSC FSC Fig.7.11 GCI Non –Terminal Mode Channel Structure 7.6.1 GCI Mode C/I Channel Handling 1) CI0 channel The Command/Indication channel 0 carries real-time status information between the W6691 and another device connected to the GCI bus interface ...

Page 50

... The microprocessor may either enforce a 1 (idle state) in “E”, “A” bit by setting the control bit MRC or MXC (MOCR register enable the control of these bits internally by the W6691 according to the Monitor channel protocol. Thus, before a data exchange can begin, the control bit MRC, or MXC should be set the microprocessor ...

Page 51

... This is effected by the microprocessor writing the “E” bit control bit MRC aborted transmission is indicated by a MAB (Monitor Channel Data Abort) interrupt Preliminary W6691 MER (Monitor Channel End Publication Release Date: Sep 2001 ...

Page 52

... Microprocessor Interface At power up, the reset pin RST# must be asserted to initialize the chip. At rising edge of RST#, data value at MBS pin determines the operation modes: HIGH for Intel bus mode, LOW for Motorola bus mode. Preliminary W6691 Publication Release Date: Sep 2001 52 ...

Page 53

... D channel transmit status D channel receive status Reserved Reserved D channel address mask 1 D channel individual SAPI 1 D channel individual SAPI 2 D channel address mask 2 D channel individual TEI 1 D channel individual TEI 2 Reserved Reserved 53 Preliminary W6691 Publication Release Date: Sep 2001 Revision 1.1 ...

Page 54

... Monitor transmit channel 0 Monitor channel 0 interrupt Monitor channel 0 control register Reserved Reserved GCI mode control/ status register Monitor receive channel 1 Monitor transmit channel 1 Monitor channel 1 interrupt Monitor channel 1 control Reserved Reserved Reserved Reserved 54 Preliminary W6691 Publication Release Date: Sep 2001 Revision 1.1 ...

Page 55

... GCI extended interrupt GCI extended interrupt mask Description Reserved Reserved Timer 1 Timer 2 Peripheral control register Peripheral I/O data register Switch function controll register Auxiliary control register 1 Auxiliary control register 2 Auxiliary control register Preliminary W6691 Publication Release Date: Sep 2001 0 Revision 1.1 ...

Page 56

... SA16 SA15 SA14 SA26 SA25 SA24 TAM6 TAM5 TAM4 TA16 TA15 TA14 TA26 TA25 TA24 VN0 LOV RBC12 RBC6 RBC5 RBC4 56 Preliminary W6691 XMS 0 XME 0 MFD L2_DLP S_RLP INT0 D_EXI B1_EXI INT0 D_EXI B1_EXI GCI ICC T1EXP GCI ICC ...

Page 57

... BAC 0 0 MSYN MAC0 MAC1 CI1R_6 CI1R_5 57 Preliminary W6691 CSEL2 CSEL1 Reserved CORD3 CORD2 CORD1 CORD0 CORD3 CORD2 CORD1 CORD0 Reserved Reserved 0 MDR0 MER0 MDA0 0 MRIE0 ...

Page 58

... CNT5 CNT4 TIDLE TCN5 TCN4 PGSWH PCRLP PXC 0 0 SRST 0 ACTL1 LC 0 INTOL 0 D_RFIFO Read Address 00H 58 Preliminary W6691 CI1X_4 CI1X_3 CI1X_2 Reserved MO0C Reserved Reserved CNT3 CNT2 CNT1 TCN3 TCN2 TCN1 ...

Page 59

... Setting this bit resets the D_ch HDLC receiver and clears the D_RFIFO data. Writing “0” to this bit has no effect. If RRST bit is set to “1” for operating “Receiver Reset” not necessary to reset RRST bit to “0” by host processor. That is to say, once RRST is set to “1”, RRST bit is reset to “0” by W6691 automatically. STT1 Start Timer 1 The timer 1 is started when this bit is set to one ...

Page 60

... CRC and the closing flag after the data transmission. Writing “0” to this bit has no effect. If XME bit is set to “1” for operating “Transmit Message End” not necessary to reset XME bit to “0” by host processor. That is to say, once XME is set to “1”, XME bit is reset to “0” by W6691 automatically. Note: If the frame 32 bytes, XME plus XMS commands must be issued at the same time ...

Page 61

... S interface. The received D channel from the S interface is not looped to transmitted D channel of S interface in this loopback function. . 8.7.5 Interrupt Status Register Value after reset : 00H D_RMR D_RME D_XFR ISTA Read_clear INT1 INT0 D_EXI 61 Preliminary W6691 Address 04H 1 0 B1_EXI B2_EXI Publication Release Date: Sep 2001 Revision 1.1 ...

Page 62

... This bit indicates that at least one interrupt bit is set in D_EXIR register. Note : A read of the ISTA register clears all bits except D_EXI, D_EXI bit is cleared when all bits in D_EXIR register are cleared RBC4 bytes of XFIFO is empty 62 Preliminary W6691 32 bytes has Publication Release Date: Sep 2001 Revision 1.1 ...

Page 63

... FIFO. If RDOV interrupt occurs, software has to reset the receiver and discard the data received. IMASK Read/Write INT1 INT0 D_EXI D_EXIR TIN2 GCI ICC T1EXP 63 Preliminary W6691 Address 05H 1 0 B1_EXI B2_EXI Read_clear Address 06H 1 0 SCC Publication Release Date: Sep 2001 Revision 1.1 ...

Page 64

... XDUN Transmit Data Underrun This interrupt indicates the D_XFIFO has run out of data. In this case, the W6691 will automatically reset the transmitter and send the inter frame time fill pattern (all 1' channel. The microprocessor must wait until transmit FIFO ready (via XFR interrupt), re-write data, and issue XMS command to re-transmit the data. ...

Page 65

... RDOV bit after reading data from D_RFIFO when RMR or RME interrupt occurs. The software must D_XSTA D_RSTA RMB Preliminary W6691 Read Address 0AH Read Address 0BH Publication Release Date: Sep 2001 Revision 1.1 ...

Page 66

... FIFO. The mask operation can be programmed by each bit respectively. The HDLC frame with SAPG and /or TEIG address are always captured and stored. D_SAM SAM3 SAM2 SAM1 66 Preliminary W6691 Read/Write Address 0EH 0 SAM0 Publication Release Date: Sep 2001 Revision 1.1 ...

Page 67

... TAM5 TAM4 Read/Write SA14 SA13 SA12 SA11 D_SAP2 Read/Write SA24 SA23 SA22 SA21 D_TAM TAM3 TAM2 TAM1 67 Preliminary W6691 Address 0FH 1 0 SA10 Address 10H 1 0 SA20 Read/Write Address 11H 1 0 TAM0 Publication Release Date: Sep 2001 Revision 1.1 ...

Page 68

... This register contains the second choice of the second byte address of received frame. For LAPD frame, TA27 - TA21 is the TEI value, TA20 Read/Write TA14 TA13 TA12 TA11 Read/Write TA24 TA23 TA22 TA21 68 Preliminary W6691 Address 12H 1 0 TA10 Address 13H 1 0 TA20 Publication Release Date: Sep 2001 Revision 1.1 ...

Page 69

... D_RFIFO. These bits are valid only after an D_RME interrupt and remain valid until the frame is acknowledged via the RACK command. D_RBCH RBC9 D_RBCL RBC3 RBC2 RBC1 69 Preliminary W6691 Read Address 16H 0 RBC8 Read Address 17H 0 RBC0 Publication Release Date: Sep 2001 Revision 1.1 ...

Page 70

... Value after reset: 00H CSEL2, CSEL1 and CSEL0 define W6691 locating in GCI channel number operated in LT-S/ LT-T mode. 8.8.2 Command/Indication Receive Register CIR Read Address 1AH Value after reset: 0FH BAS Bus Access Status Indicate the state of the TIC –bus: 1: W6691 itself occupies the D and C/I channel ...

Page 71

... BAC Bus Access Control It is available if TIC bus function is active. If this bit is set to “1”, W6691 will try to access the TIC-bus to occupy the C/I channel even channel frame has to be transmitted. It should be reset when the access has been completed to grant a similar access to the other devices transmitting in that GCI channel. ...

Page 72

... Monitor Transmit Channel 0 Value after reset: FFH bit positions in frames and 16 frame 1 and MO0X Read/Write Preliminary W6691 Address 21H 1 0 Publication Release Date: Sep 2001 Revision 1.1 ...

Page 73

... Monitor Channel 0 Receive Interrupt Enable Monitor channel interrupt status MDR0, MER0 generation is enabled (1) or masked (0). MO0I MDR0 MER0 MDA0 MO0C MRE0 MRC0 MIE0 73 Preliminary W6691 Read_clear Address 22H 1 0 MAB0 Read/Write Address 23H 1 0 MXC0 Publication Release Date: Sep 2001 Revision 1.1 ...

Page 74

... In addition, the MDR0 interrupt is blocked, except for the first byte of a packet (if MRE0=1). 1: “E” bit is internally controlled by the W6691 according to Monitor channel protocol. In addition, the MDR0 interrupt is enabled for all received bytes according to the Monitor channel protocol (if MRE0=1) ...

Page 75

... Monitor Transmit Channel 1 Register MO1X Read/Write Address 28H Value after reset: FFH Contains the Monitor channel data transmitted in GCI Monitor channel 1 according to the Monitor channel protocol Preliminary W6691 Publication Release Date: Sep 2001 Revision 1.1 ...

Page 76

... In addition, the MDR1 interrupt is blocked, except for the first MRE1=1 MDR1 MER1 MDA1 MO1C MRE1 MRC1 MIE1 76 Preliminary W6691 1 0 MAB1 Read/Write Address 2AH 1 0 MXC1 byte of a packet (if Publication Release Date: Sep 2001 Revision 1.1 ...

Page 77

... W6691 according to Monitor channel protocol. In addition, the MDR1 interrupt is enabled for all received bytes according to the Monitor channel protocol (if MRE1=1). MIE1 Monitor channel 1 Transmit Interrupt Enable Monitor interrupt status MDA1, MAB1 generation is enabled (1) or masked (0). ...

Page 78

... It is only used in TE-mode. 8.8.18 GCI Extended Interrupt Mask Register Value after reset: F7H GCI_EXIR MO1C MO0C 0 GCI_EXIM MO1C Preliminary W6691 Read_clear Address 34H CI1 Read/Write Address 35H CI1 Publication Release Date: Sep 2001 Revision 1.1 ...

Page 79

... C/I command "ECK" must be issued in addition to the STT1 command to start the timer. Note: The timer is stopped when it expires in Single Count Down Mode(T1MD=0) or TIMR1 register is re- written in both mode CNT3 CNT2 CNT1 79 Preliminary W6691 0 CNT0 Publication Release Date: Sep 2001 Revision 1.1 ...

Page 80

... This bit defines value of TOUT2 pin when timer is off. That is to say, the TIDLE determine the TOUT2 pin level is high or low when timer2 is off. TCN5-0 Timer 2 Count Value 0: Timer is off 63: Timer count value in unit of ms TCN3 TCN2 TCN1 80 Preliminary W6691 0 TCN0 Publication Release Date: Sep 2001 Revision 1.1 ...

Page 81

... Pin IO1's output driver is enabled. OE0 Direction Control for IO0 0 : Pin IO0's output driver is disabled and input driver is enabled 1 : Pin IO0's output driver is enabled. Read/Write Address 3AH OE3 OE2 81 Preliminary W6691 1 0 OE1 OE0 Publication Release Date: Sep 2001 Revision 1.1 ...

Page 82

... IO0 Read or Write Data of Pin IO0 On read operation, the present value of pin IO0 is read. On write operation, the data is driven to pin IO0 only if PCTL:OE0=1. PIODR IO3 IO2 IO1 82 Preliminary W6691 Read/Write Address 3BH 0 IO0 Publication Release Date: Sep 2001 Revision 1.1 ...

Page 83

... Select B2 channel switch between Layer2 and Layer1/GCI. 01: Select B2 channel switch between Layer1/GCI and PCM. 10: Select B2 channel switch between PCM and Layer2 PXC B2SW1 Connection B1, PCM2 B2 B2, PCM2 B1 83 Preliminary W6691 Address 3CH B2SW0 B1SW1 B1SW0 Publication Release Date: Sep 2001 Revision 1.1 ...

Page 84

... PD Power Down After hardware reset or software rest, PD bit is set to “0”. It means W6691system clock is powered up after reset. 0: Power Down Disable. W6691 system clock is not allowed to be powered down. 1: Power Down Enable interface can not receive non info 0 signal from line, W6691 enter power down mode automatically ...

Page 85

... LED Controlled If ACLTS1is set to “1”, LC bit is programmable by microprocessor shows ACTLS1 pin is driven to high level shows ACTLS1 pin is driven to low level. SPU: Software Power UP If SPU is set to “1”, W6691 can awaked from power down mode. Read/Write SPU ...

Page 86

... B1 channel address mask 1 B1 channel address mask 2 B1 channel address 1 B1 channel address 2 B1 channel receive frame byte count low B1 channel receive frame byte count high B1 channel transmit idle pattern 86 Preliminary W6691 Address 3FH Publication Release Date: Sep 2001 Revision 1.1 ...

Page 87

... MA14 MA26 MA25 MA24 RA16 RA15 RA14 RA26 RA25 RA24 RBC6 RBC5 RBC4 0 0 LOV RBC12 RBC11 IDLE6 IDLE5 IDLE4 B1_RFIFO B1_XFIFO 87 Preliminary W6691 XMS XME XRST B1_128 SW56 FTS1 FTS0 0 0 XFR XDUN 1 1 XFR XDUN 0 XDOW 0 XBZ ...

Page 88

... This bit is write-only. It's auto-clear. Writing “0” to this bit has no effect. If XMS bit is set to “1” for operating “Transmit Message Start/Continue” not necessary to reset XMS bit to “0” by host processor. That is to say, once XMS is set to “1”, XMS bit is reset to “0” by W6691 automatically. XME Transmit Message End In transparent mode, setting this bit indicates the end of the whole frame transmission ...

Page 89

... LOW to save power. This bit is read/write. Read operation returns the previously written value. Note: The receiver is deactive after hardware reset or software reset. B1_MODE Read/Write XACT B1_128K SW56 89 Preliminary W6691 Address 1 0 FTS1 FTS0 Publication Release Date: Sep 2001 54H Revision 1.1 ...

Page 90

... FTS1 FTS0 8.11.5 B1_ch Extended Interrupt Register B1_EXIR Value after reset: 00H RMR RME RDOV Threshold (byte) 64 Reserved 96 Not allowed XFR 90 Preliminary W6691 Read_clear Address 56H 0 XDUN Publication Release Date: Sep 2001 Revision 1.1 ...

Page 91

... XDUN Transmit Data Underrun This interrupt occurs when the B1_XFIFO has run out of data. In this case, the W6691 will automatically reset the transmitter and send the inter frame time fill pattern on B channel. The software must wait until transmit FIFO ready condition (via XFR interrupt), re-write data, and issue XMS command to re-transmit the data. ...

Page 92

... Used in transparent mode only. These bits mask the first byte address comparisons. If the mask bit is "1", the corresponding bit comparison with B1_ADR1 is disabled. 0: Unmask comparison 1: Mask comparison B1_ADM1 MA13 MA12 MA11 92 Preliminary W6691 Read/Write Address 0 MA10 Publication Release Date: Sep 2001 59H Revision 1.1 ...

Page 93

... RA14 RA13 RA12 RA11 Read/Write RA24 RA23 RA22 RA21 RBC3 RBC2 RBC1 93 Preliminary W6691 Read/Write Address 5AH 1 0 MA20 Address 5BH 1 0 RA10 Address 5CH 1 0 RA20 Read Address 5DH 1 0 RBC0 Publication Release Date: Sep 2001 Revision 1.1 ...

Page 94

... This pattern is transmitted when the transmitter is active and transmit FIFO is empty. Valid in extended transparent mode only RBC9 if remainder remainder = 0 B1_IDLE IDLE3 IDLE2 IDLE1 94 Preliminary W6691 Read Address 5EH 0 RBC8 8192 bytes. This bit is valid Read/Write Address 5FH 0 IDLE0 Publication Release Date: Sep 2001 Revision 1.1 ...

Page 95

... B2 channel receive frame byte count high B2 channel transmit idle pattern Reserved RRST 0 0 ITF RACT XACT Reserved 0 RMR RME RDOV 95 Preliminary W6691 XMS XME XRST 0 SW56 FTS1 FTS0 0 0 XFR XDUN Publication Release Date: Sep 2001 Revision 1.1 ...

Page 96

... MA15 MA14 MA26 MA25 MA24 RA16 RA15 RA14 RA26 RA25 RA24 RBC6 RBC5 RBC4 0 0 LOV RBC12 RBC11 IDLE6 IDLE5 IDLE4 96 Preliminary W6691 1 1 XFR XDUN 0 XDOW 0 XBZ MA13 MA12 MA11 MA10 MA23 MA22 MA21 MA20 RA13 RA12 RA11 RA10 RA23 ...

Page 97

... S/T layer 1 in state “F3 DDA Deactivated without clock” 6 =5V, S/T layer 1 in state “F7 DD Activated” < < Preliminary W6691 Remarks < All pins except IN DD SX1,2, SR1,2 < All pins except OUT DD ...

Page 98

... SR1 XTAL1,2 Symbo Values l f 7.680 Max. 100 C Max Fundamental depends on the crystal specification. The typical values are pF. 98 Preliminary W6691 SX1,2, SR1,2 1) SX1 SX1,2 SX1,2 = Unit MHz ppm pF Publication Release Date: Sep 2001 Revision 1.1 ...

Page 99

... Note 1: These drawings are not to scale. 2: The frequency of PBCK is 1536 kHz which includes 24 channels of 64 kbps data. The PFCK1 and PFCK2 are located at channel 1 and channel 2, each with PBCK duration. Max. 2:1 24 CHs Port2 99 Preliminary W6691 Port1 Port2 Port2 Port1 Publication Release Date: Sep 2001 Revision 1.1 ...

Page 100

... S/T clock. This shift is made on the LOW level time of PBCK and the HIGH level time is not affected. This introduces jitters on the PBCK, PFCK1 and PFCK2 with jitter amplitude 260 ns (peak-to-peak) and jitter frequency about 2.67~4 kHz. ta8 MIN. NOMINAL 195 100 Preliminary W6691 ta5 ta6 MAX. REMARKS 325 Unit = nS 325 455 20 20 ...

Page 101

... Microprocessor Timing Intel mode read cycle timing t1 ALE t2 A<7:0> AD<7:0> CS# RD# Intel mode write cycle timing t1 ALE t2 A<7:0> AD<7:0> CS# WR D<7:0> t15 t3 D<7:0> t14 t4 t12 101 Preliminary W6691 t10 A<7:0> t11 t10 A<7:0> t13 Publication Release Date: Sep 2001 Revision 1.1 ...

Page 102

... Motorola mode read cycle timing A<7:0> t16 CS# t18 DS# t22 RW D<7:0> Motorola mode write cycle timing A<7:0> t16 CS# t18 DS# t25 RW D<7:0> t17 t19 t21 t20 t23 t24 t17 t19 t27 t26 t28 t29 102 Preliminary W6691 Publication Release Date: Sep 2001 Revision 1.1 ...

Page 103

... Data output delay from DS# t24 Data hold time from DS# t25 RW setup time to DS# write t26 DS# write pulse width t27 DS# write recovery time t28 Write data setup time to DS# t29 Write data hold time from DS# Preliminary W6691 MIN. MAX 110 ...

Page 104

... Test Point 0.8 0.4 10. ORDERING INFORMATION PART NUMBER PACKAGE TYPE W6691CD 64-pin LQFP W6691CP 68-pin PLCC 2.0 Device Under Test 0.8 PRODUCTION FLOW Commercial +70 Commercial +70 104 Preliminary W6691 C = 150pF load Publication Release Date: Sep 2001 Revision 1.1 ...

Page 105

... Min. Nom. Max. Min. A 0.063 A 0.002 0.05 1 0.006 A 0.053 0.055 0.057 1. 0.007 0.008 0.011 0.17 c 0.09 0.004 0.008 D 0.393 E 0.393 e 0.020 H 0.472 D H 0.472 E L 0.024 0.030 0.018 0.45 L 0.039 1 y 0.003 3 105 Preliminary W6691 Nom. Max. 1.60 0.15 1.40 1.45 0.20 0.27 0.20 10.00 10.00 0.50 12.00 12.00 0.75 0.60 1.00 0.08 3.5 7 Publication Release Date: Sep 2001 Revision 1.1 ...

Page 106

... FAX: 886-2-27197502 FAX: 886-2-27197502 Note: All data and specifications are subject to change withou t notice. Note: All data and specifications are subject to change withou t notice. Preliminary W6691 Winbond Electronics North America Corp. Winbond Electronics North America Corp. Winbond Memory Lab. ...

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