w6694 Winbond Electronics Corp America, w6694 Datasheet
w6694
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w6694 Summary of contents
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... The information described in this document is the exclusive intellectual property of Winbond Electronics Corp and shall not be reproduced without permission from Winbond. Winbond is providing this document only for reference purposes for W6694-based system design. Winbond assumes no responsibility for errors or omissions. All data and specifications are subject to change without notice ...
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... Layer 1 Command/Indication Register CIX Read/Write Address 04h......................... 22 8.2.6 U-layer1 Ready Code 8.3 GCI Mode Registers ............................................................................................................... 22 8.3.1 GCI Mode Command Register 8.3.2 Monitor Channel Control Register 8.3.3 Monitor Channel Receive Register MOR Read Address 08h .................................... 24 Preliminary W6694 ISTA Read_clear............................................................... 18 MOIR Read_clear................................................. 19 PICR Read_clear .......................................................... 19 IMASK Read/Write Address 00h.......................................... 19 CMDR1 Write Address 01h.................................................... 20 CMDR2 Write Address 02h ...
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... ORDERING INFORMATION...................................................................................................... 32 11. PACKAGE INFORMATION ...................................................................................................... 33 48L LQFP ( 1.4 mm footprint 2.0 mm) ............................................................................... 33 PIE Read/Write Address 0Ah ......................................... 24 PO1 Read/Write Address 0Bh ............................................. 24 PO2 Read/Write Address 0Ch ............................................. 25 PDATA Read Address 0Dh........................................................ 25 PCM1RS Read/Write Address 12h.......................... 26 PCM2RS Read/Write Address 13h.......................... 27 Publication Release Date: October 2000 - 3 - Preliminary W6694 Revision A1 ...
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... GENERAL DESCRIPTION The Winbond's single chip USB bus ISDN S/T interface controller W6694 is an all-in-one device suitable for ISDN Internet access. The integrated USB and ISDN design provides low cost, pure passive solution for USB-IDSN application. W6694 also provides two PCM CODEC interfaces for the ability to access ISDN through voice channel ...
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... FIG.3.1 W6694 Pin Out Publication Release Date: October 2000 - 5 - Preliminary W6694 VDD23 23 VSS23 22 TEST2 21 TEST1 20 EPDO 19 EPDI 18 EPSK 17 EPCS 16 PRXD 15 PTXD 14 VDD22 ...
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... PIN DESCRIPTION Table 4.1 W6694 Pin Descriptions SYMBOL PIN NO UCLK1 41 UCLK2 42 ISDN Signals and External Crystal SR1 45 SR2 46 SX1 48 SX2 1 XTAL1 2 XTAL2 3 GCIDCL 6 GCIFSC 7 GCIDD 8 GCIDU 9 PFCK1 10 PFCK2 11 PBCK 12 PTXD 15 PRXD 16 I/O FUNCTION USB Bus I/O USB D+ data line. I/O USB D- data line. ...
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... IO pin capable of driving LED. I/O I/O I/O I/O I/O I/O I/O Others I External reset. Cause internal circuit reset. Internal 10k ohm pull-up is provided. I Test mode enable. Connected to HIGH for normal operation. O USB suspended. Active HIGH NC No connection. Internal pull-up is provided. Publication Release Date: October 2000 - 7 - Preliminary W6694 Revision A1 ...
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... ISDN1 ISDN CONNECTOR 2 W6694 WITH USB & ISDN INTERFACE W6694 DEMO BOARD-DATA ONLY Size Document Number 15.20X12.00 D:\..\W6694_DEMO\W6694_DEMO.DSN\W6694.SCH Date: Monday, May 29, 2000 Sheet LED LED LED R20 R21 R22 560 ...
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... BLOCK DIAGRAM S/T Interface GCI GCI Bus Control PCM PCM Port Codec Control Interface 7. FUNCTIONAL DESCRIPTIONS 7.1 USB Descriptions TAble 7.1 W6694 all USB Endpoints END TYPE DIRECTION* POINT 0 Control IN/OUT 1 Bulk OUT 2 Bulk IN 3 Interrupt IN 4 Isoch. OUT 5 Isoch Direction: IN – device to host, OUT – host to device ...
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... USB standard requests are supported by W6694, and W6694 will respond to requests according to USB specification revesion 1.1. These includes “CLEAR_FEATURE, GET_CONFIGURATION, GET_DESCRIPTOR, GET_INTERFACE, GET_STATUS, SET_ADDRESS, SET_CONFIGURATION, SET_DESCRIPTOR, SET_FEATURE, SET_INTERFACE”. The “SYNC_FRAME” request is not supported. 7.1.1 Control-IN Transactions (Endpoint 0) 7.1.1.1 Get Device Descriptor OFFSET ...
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... Alternate Interface 0 Descriptor Endpoint 1 Descriptor 0008 1 00 Endpoint 2 Descriptor 0008 1 00 Publication Release Date: October 2000 - 11 - Preliminary W6694 REMARK OUT Bulk IN Bulk Revision A1 ...
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... Note: After W6694 is successfully enumerated by the USB host, software must issue SET_INTERFACE request with alternate setting 1, to enable all endpoints. When in default state (alternate setting 0), only endpoint 0 is functioning. 7.1.1.3 Get String Descriptor 0 OFFSET FIELD 0 bLength 1 bDescriptorType ...
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... On received this request from host, W6694 will not detect the incoming ISDN broadcast message. 7.1.2.2 Device Set Feature, Remote Wake-up BmRequestType bRequest 00H SET_FEATURE On received this request from host, W6694 will detect the incoming ISDN broadcast message. This is default setting. 7.1.2.3 Set Interface 0, Alternate Setting 0 bmRequestType bRequest 01H SET_INTERFACE On received this request from host, all endpoints except endpoint 0 are disabled ...
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... Interrupt-IN endpoint is used to periodically poll device interrupt data. W6694 use this endpoint to report interrupt status of all interrupt sources. All four bytes data of interrupt registers will be sent to host if ISTA is not interrupt is detected by W6694 when received Interrupt-IN token, A NAK token will return to the USB host. ...
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... These bits indicate the data length of the subsequent data for D channel. The typical value channel message is sending message to send. Once the opening flag of D channel message is sent, W6694 will move the data in D-XFIFO to S interface at the rate of 16K bps. The software must carefully assign proper length for each packet, otherwise a D-XFIFO under-run or overflow condition may occur ...
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... It is set when XFIFO has at least half of the XFIFO size available for incoming USB data. XDUN Transmit Data Under-run The corresponding XFIFO has run out of data. For D and B channel, the XFIFO is reset and disabled for that channel. This bit is cleared when XFIFO is enabled by XEN bit. Preliminary W6694 ...
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... Configuration EEPROM A 9346/93C46 type serial EEPROM can be used to store customized USB device configuration data. These configuration data will be read by W6694 after power on or reset, and sent to the USB host during enumeration. If EEPROM is not presented, or the first 16 bits in EEPROM is FFFFh, the default value in W6694 will be sent to the USB host instead. ...
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... Layer 1 Command/Indication Register CIR Value after reset: 0Fh CIR3-0 Layer 1 Indication Code Value of the received layer 1 indication code for S/T interface. Note these bits have a buffer size of two. Preliminary W6694 Contents 15 0 Vendor ID Device ID Device release number ISTA Read_clear 4 3 ...
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... Descriptions DC 1111 Idle code on GCI interface PU 0111 U transceiver power up MOIR MDR MER MDA PICR Read_clear IMASK Read/Write Address 00h Publication Release Date: October 2000 - 19 - Preliminary W6694 Read_clear 1 0 MAB Revision A1 ...
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... S bus is not connected or if there is no signal on the S bus. In this case, the C/I command ECK must be issued to enable loopback function. This bit remains set, until cleared by software reset (SRST). CMDR1 Write Address 01h DREN SRST CISOE - 20 - Preliminary W6694 1 0 DLP RLP ...
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... These two bits select the output phase delay compensation. OPS1 OPS0 output phase delay compensation 0 1 Output phase delay compensation 260 Output phase delay compensation 520 Output phase delay compensation 1040 nS Preliminary W6694 CMDR2 Write Address 02h B1REN B2XRST B2RRST CTL Read/Write ...
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... The previous transmission is in progress. Read/Write CIX3 CIX2 CIX1 Code Descriptions AR 1000 Activate request command L1_RC Read/Write Address 05h RC3 RC2 RC1 GCR Read/Write TLP GRLP SPU Preliminary W6694 Address 04h 1 0 CIX0 1 0 RC0 Address 06h ...
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... After U transceiver power down, W6694 will receive the indication DC (Deactivation Confirmation) from GCI bus and then software has to set SPU acknowledge U transceiver, by pulling GCIDU line to HIGH. W6694 remains normal operation Setting SPU 1, PD enforce connected layer 1 devices (U transceiver) to deliver GCI bus clocking. ...
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... Value after reset: FFh OM3_1 OM3_0 OM2_1 MOR Read MOX Read/Write PIE Read/Write IE4 IE3 IE2 IE1 PO1 Read/Write OM2_0 OM1_1 OM1_0 - 24 - Preliminary W6694 Address 08h 1 0 Address 09h 1 0 Address 0Ah 1 0 IE0 Address 0Bh 1 0 OM0_1 OM0_0 ...
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... USB B1 PO2 Read/Write OM6_0 OM5_1 OM5_0 PDATA Read L1B1RS Read/Write RS2 RS1 Publication Release Date: October 2000 - 25 - Preliminary W6694 Address 0Ch 1 0 OM4_1 OM4_0 Address 0Dh 0 D0 Address 0Eh 0 RS0 Revision A1 ...
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... These bits select the source where USB B2 channel will receive data from. Possible values are: 000 (0): receive from PCM1 001 (1): receive from PCM2 011 (3): receive from Layer1 B2 101 (5): receive from USB B2 8.5.5 PCM1 Receiver Select Register Value after reset: 00h Preliminary W6694 L1B2RS Read/Write RS2 RS1 USBB1RS Read/Write 4 ...
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... Absolute Maximum Rating PARAMETER Voltage on Any Pin with Respect to Ground Ambient Temperature Under Bias Maximum Voltage Note: Exposure to conditions beyond those listed under Absolute Maximum Ratings may adversely affect the life and reliability of the device. Preliminary W6694 PCM2RS Read/Write ...
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... Output Pulse 2.10 Amplitude ( SX2 SX1 Transmitter I 7.5 X Output Current Transmitter Output 23 Impedence 1) Note: Due to the transformer, the load resistance seen by the circuit is four times R Preliminary W6694 MIN. TYP. MAX. UNIT 4.75 5.0 5.25 3 SSD MAX. UNIT TEST CONDITIONS 0 +0.4 0.4 ...
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... C 10 OUT External XTAL1 oscillator signal or 7.68MHz C 50pF L XTAL2 N.C. SYMBOL VALUES f 7.680 Max. 100 C Max Fundamental MAX. 2:1 Publication Release Date: October 2000 - 29 - Preliminary W6694 UNIT REMARKS pF SX1 SR1 XTAL1, 2 XTAL1 XTAL2 UNIT MHz ppm pF Revision A1 ...
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... Note 2: The frequency of PBCK is 1536 kHz which includes 24 channels of 64 kbps data. The PFCK1 and PFCK2 are located at channel 1 and channel 2, each with PBCK duration. Detailed PCM timing ta1 ta2 PBCK ta3 PFCK1 PFCK2 ta4 PTXD ta7 PRXD 24 CHs ta8 - 30 - Preliminary W6694 Port Port2 1 Port Port 2 1 ta5 ta6 ...
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... PARAMETER DESCRIPTIONS tb1 EPSK low tb2 EPSK high tb3 EPCS output delay tb4 EPSD output delay tb5 EPSD tri-state delay tb6 EPSD input setup time tb7 EPSD input hold time Preliminary W6694 MIN. NOMINAL 325 195 325 tb6 tb5 ..... D15 A5 A4 ...
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... D 7.00 0.272 0.276 0.280 6.90 E 0.272 0.280 6.90 7.00 0.276 e 0.014 0.020 0.026 0.35 0.50 H 0.350 0.358 8.90 0.354 9. 0.350 0.354 0.358 8.90 9. 0.024 0.030 0.45 0.60 0.018 L 0.039 1. 0.004 Preliminary W6694 Max. 0.15 1.45 0.25 0.20 7.10 7.10 0.65 9.10 9.10 0.75 0.10 7 ...
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... FAX: 886-2-27197502 FAX: 886-2-27197502 Note: All data and specifications are subject to change withou t notice. Note: All data and specifications are subject to change withou t notice. Preliminary W6694 Winbond Electronics North America Corp. Winbond Electronics North America Corp. Winbond Memory Lab. ...