hyb514100bj-60 Infineon Technologies Corporation, hyb514100bj-60 Datasheet

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hyb514100bj-60

Manufacturer Part Number
hyb514100bj-60
Description
Manufacturer
Infineon Technologies Corporation
Datasheet

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Company
Part Number
Manufacturer
Quantity
Price
Part Number:
HYB514100BJ-60
Manufacturer:
MARVELL
Quantity:
5
Part Number:
HYB514100BJ-60
Manufacturer:
SIEMENS
Quantity:
7 587
4M
Advanced Information
• 4 194 304 words by 1-bit organization
• 0 to 70 C operating temperature
• Fast Page Mode Operation
• Performance:
• Single + 5 V ( 10 %) supply with a built-in
• Low power dissipation
• Standby power dissipation:
• Output unlatched at cycle end allows two-dimensional chip selection
• Read, write, read-modify write, CAS-before-RAS refresh, RAS-only refresh,
• All inputs and outputs TTL-compatible
• 1024 refresh cycles/16 ms
• Plastic Packages: P-SOJ-26/20-2 with 300 mil width
Semiconductor Group
t
t
t
t
t
max. 660 mW active (-50 version)
max. 605 mW active (-60 version)
11 mW max. standby (TTL)
5.5 mW max. standby (CMOS)
hidden refresh and test mode capability
RAC
CAC
AA
RC
PC
1-Bit Dynamic RAM
RAS access time
CAS access time
Access time from address
Read/Write cycle time
Fast page mode cycle time
-50
50
13
25
95
35
V
110 ns
-60
60
15
30
40
BB
1
generator
ns
ns
ns
ns
HYB 514100BJ-50/-60
1998-10-01

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hyb514100bj-60 Summary of contents

Page 1

Dynamic RAM Advanced Information • 4 194 304 words by 1-bit organization • operating temperature • Fast Page Mode Operation • Performance: t RAS access time RAC t CAS access time CAC t Access ...

Page 2

... P-SOJ-26/20-2 300 mil P-SOJ-26/20-2 300 mil P-SOJ-26/20 RAS 3 24 CAS N. N.C. A10 SPP02808 2 HYB 514100BJ-50/- DRAM Descriptions DRAM (access time 50 ns) DRAM (access time 60 ns) 1998-10-01 ...

Page 3

... A6 Refresh Counter (10 A10 Row 11 Address Buffers (11) No.1 Clock RAS Generator Block Diagram Semiconductor Group 10 10 Row Decoder 3 HYB 514100BJ-50/- DRAM Data In DI Buffer DO Data Out Buffer 11 Column Decoder Sense Amplifier I/O Gating 4096 . . . Memory Array 1024 . . . V Substrate Bias CC Generator V SS ...

Page 4

... HYB 514100BJ-50/-60 4M Limit Values Unit Test min. max. V 2 – 1.0 0.8 V 2.4 – V – 0.4 V – – – 120 mA – 110 mA – – 120 mA – 110 mA – – DRAM Condition 1998-10-01 ...

Page 5

... DRAM Condition 1 2 Unit 1998-10-01 ...

Page 6

... WCS t 13 RWL t 13 CWL 115 RWC t 50 RWD t 13 CWD t 25 AWD 6 HYB 514100BJ-50/- DRAM Limit Values Unit Note -50 -60 – 5 – – – – – – 30 – ...

Page 7

... CPWD t 10 CSR t 10 CHR t 5 RPC t 10 WRP t 10 WRH t 35 CPT t 10 WTS t 10 WTH 7 HYB 514100BJ-50/- DRAM Limit Values Unit Note -50 -60 – 40 – ns – 10 – – 200k 60 200k ns – 35 – ns – 60 – ns – 35 – ...

Page 8

... RCD (MAX.) t limit, then access time is RCD (MAX.) t can be met. is specified as RAD (MAX.) t limit, then access time is RAD (MAX.) , the cycle is an early write cycle WCS (MIN.) t > the cycle is a read- CPWD CPWD (MIN.) 1 DRAM 1998-10-01 ...

Page 9

... Semiconductor Group RAS t CSH t t RCD RSH t CAS t t RAD RAL t t CAH ASC Column Address t RAH t RCS CAC t CLZ RAC 9 HYB 514100BJ-50/- DRAM CRP t ASR Row Address t RCH t RRH t OFF Hi Z Valid Data OUT SPT03013 1998-10-01 ...

Page 10

... Write Cycle (Early Write) Semiconductor Group RAS t CSH t t RCD RSH t CAS t t RAD RAL t t CAH ASC Column Address t CWL t WCS WCH t RWL Valid Data HYB 514100BJ-50/- DRAM CRP t ASR Row Address SPT03014 1998-10-01 ...

Page 11

... RCD t RAH t CAH t ASC Column Address t AWD t t RAD CWD t RWD RCS t CAC t CLZ t RAC 11 HYB 514100BJ-50/- CAS CRP t RSH t ASR Address t CWL t RWL Valid Data IN t OFF Data OUT 1 DRAM Row SPT03015 1998-10-01 ...

Page 12

... AWD Data IN Data IN t CPA t CLZ CLZ t t CAC CAC t OFF Data OUT Data OUT 12 HYB 514100BJ-50/- DRAM t t RSH t t CAS CRP t RAL t CAH t ASC Column Address t t CPWD RWL t CWD t CWL t AWD ...

Page 13

... Column Address Address t RCH t RCS t t RAC CPA CAC CAC t OFF t t CLZ CLZ Valid Data OUT 13 HYB 514100BJ-50/- DRAM RHCP CRP t RSH t CAS t CAH t ASR t ASC Column Row Address Address t RCH t RCS t RRH t CPA t ...

Page 14

... Address t t CWL t CWL WCS t t WCH WCH Valid Valid Data IN Data HYB 514100BJ-50/- DRAM RSH t CRP t CAS t RAL t CAH t t ASC ASR Column Row Address Address t RWL t t CWL WCS t WCH ...

Page 15

... V IH RAS CAS ASR V IH Row A0 - A10 Address (Output "H" or "L" RAS-Only Refresh Cycle Semiconductor Group RAS t RAH HYB 514100BJ-50/- DRAM CRP t RPC t ASR Row Address SPT03019 1998-10-01 ...

Page 16

... RAS RPC CAS WRP OFF (Output "H" or "L" CAS-Before-RAS Refresh Cycle Semiconductor Group t RAS t CSR t CHR t WRH 16 HYB 514100BJ-50/- DRAM CRP t RPC Hi Z 1998-10-01 SPT03020 ...

Page 17

... Hidden Refresh Cycle (Read) Semiconductor Group RAS RP t RCD RSH t WRP t CAH Column Address t RRH CAC t CLZ t RAC Valid Data OUT 17 HYB 514100BJ-50/- RAS CHR CRP t WRH t ASR Address t OFF Hi Z 1998-10-01 1 DRAM Row SPT03021 ...

Page 18

... V OL "H" or "L" Hidden Refresh Cycle (Early Write) Semiconductor Group RAS RP t RSH t CAH Column Address t WCH Valid Data HYB 514100BJ-50/- DRAM RAS CHR CRP t ASR Row Address SPT03022 1998-10-01 ...

Page 19

... Z t AWD t t CWD RCS t WRH t CAC CLZ t CAC 19 HYB 514100BJ-50/- RSH t CAS t RAL t ASR Row Address t RRH t RCH t OFF Valid Data OUT RWL t CWL t RWL Data IN t OFF Valid Data OUT SPT03023 1 DRAM 1998-10-01 ...

Page 20

... If any of the bits differ, the data output pin indicates a “0”. In Test Mode the 4M DRAM can be tested were a 512K DRAM. Test Mode is exited by any refresh operation which is not a WE, CAS-before-RAS cycle. Addresses A10R, A10C and A0C do not care during Test Mode ...

Page 21

... Index Marking Sorts of Packing Package outlines for tubes, trays etc. are contained in our Data Book “Package Information”. SMD = Surface Mounted Device Semiconductor Group 0.1 0.2 20x 0. -0. HYB 514100BJ-50/- DRAM 7.75 -0.25 B 6.8 ±0.3 0.25 B 8.63 -0.25 0.18 B GPJ09100 Dimensions in mm 1998-10-01 ...

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