at572d740 ATMEL Corporation, at572d740 Datasheet

no-image

at572d740

Manufacturer Part Number
at572d740
Description
Diopsis 740 Dual Core Dsp
Manufacturer
ATMEL Corporation
Datasheet
Features
Dual Core System Integrating an ARM7TDMI ARM
mAgic DSP for Audio, Communication and Beam-forming Applications
High Performance DSP Operating at 100 MHz
Utilizes the ARM7TDMI Processor Core with 32 K Byte of Integrated SRAM,
Operating at 50 MHz
Efficient ARM - DSP Interface Based on 1K x 40-bit Dual Ported Shared Memory,
Memory Mapped Register Access, and Interrupt Lines
1.8 V Core Operating Voltage, 3.3 V I/O Operating Voltage
On-chip PLL for 100 Mhz Operation from 25 Mhz Reference Clock
352-ball PBGA Package
– 1 GFLOPS - 1.5 Gops
– 10 Arithmetic Operations per Cycle (4 Multiply, 2 Add/subtract, 1 Add, 1 Subtract
– Native Support for Complex Arithmetic and Vectorial SIMD Operations: One
– 32-bit Integer and IEEE 40-bit Extended Precision Floating Point Numeric Format
– Large Multi-port Data Register File: 512 Registers Organized in Two 4-input 4-
– Orthogonal VLIW Architecture, Code Compression for Code Size Reduction
– Flexible Addressing Capability: 2 Independent Address Generation Units
– 1.7 Mbits of On-chip SRAM:
– DMA Access to the External Program and Data Memory
– Two Main Operating Modes: Run and System Mode
– Efficient Optimizing Assembler: Allows Easy Exploitation of the Available
– Fully-programmable External Bus Interface (EBI)
– 8-channel Peripheral Data Controller (PDC)
– 8-level Priority, Individually Maskable Vectored Interrupt Controller
– 28 Programmable I/O Lines
– 8-channel 11-bit Programmable Clock Prescaler Feeding the Timer, Watchdog,
– 3-channel 16-bit Timer/Counter
– 2 USARTs
– 2 Master/Slave SPI Interfaces
– Programmable Watchdog Timer
– ADDA (A/D and D/A Converters) Interface Supporting up to 4 Analog to Digital and
– IEEE 1149.1 JTAG Boundary Scan on all Active Pins
Floating and Fixed Point) Allowing Single Cycle FFT Butterfly
Complex Multiply with Dual Add/sub per Clock Cycle or Two Real Multiply and Two
Add/sub or Simple Scalar Operations
output 256-register Banks
Operating on a 16 Registers Address Register File Supporting Programmable
Stride, Circular Pointers and Bit Reversal
Hardware Resources Parallelism
USARTs, SPIs
4 Digital to Analog, Stereo 24-bit Converters
17 K x 40-bit Data Memory Locations
8 K x 128-bit Program Memory Location, Equivalent to 24K Instructions
Maximum External Address Space of 4 M Bytes
Up to 4 Chip Selects
Software-programmable 8/16-bit External Data Bus
4 External, 20 Internal Interrupt Sources, Including a High-priority, Low-latency
Interrupt Request
5 Internal Clock Sources and 3 Configurable Sources (External Source or
Cascaded Timer Configuration)
2 Multi-purpose Output Pins plus 1 Output Dedicated to the ADDA Interface plus
3 Outputs Dedicated to the mAgic DSP
2 Dedicated Peripheral Data Controller (PDC) Channels per USART
1 USART Supporting Full Modem Interface
2 Dedicated Peripheral Data Controller (PDC) Channels per SPI
8- to 16-bit Programmable Data Length
4 External Slave Chip Selects for each SPI
Thumb
Processor Core and a
Note: This is a summary document. A complete document
is not available at this time. For more information, please
contact your local Atmel sales office.
DIOPSIS 740
Dual Core DSP
AT572D740
Summary
7001AS–DSP–03/04

Related parts for at572d740

at572d740 Summary of contents

Page 1

... PBGA Package   Thumb Processor Core and a Note: This is a summary document. A complete document is not available at this time. For more information, please contact your local Atmel sales office. DIOPSIS 740 Dual Core DSP AT572D740 Summary 7001AS–DSP–03/04 ...

Page 2

... Description AT572D740 2 DIOPSIS 740 is a Dual CPU Processor integrating a mAgic DSP and an ARM7TDMI™ RISC MCU, plus a total of 245 Kbytes SRAM. The system combines the flexibility of the ARM7TDMI RISC controller with the very high performance of the DSP. mAgic is a high performance VLIW DSP delivering 1 Giga floating-point operations per second (GFLOPS clock rate of 100 MHz ...

Page 3

... PLL_LFT M24 PLL_LOCK M26 PLL_TST (dnc) AB23 PLL_UP (dnc) AB25 RESET AC26 SCAN_EN (dnc) AC24 SCAN_TEST (dnc) AC25 SINGLE 1. PIO[5] AD26 SPI0_MISO AT572D740 Ball Name Ball AD23 SPI0_NSS[1] A17 AE24 SPI0_NSS[2] D17 AD22 SPI0_NSS[3] B16 AC22 SPI0_SCK D18 AE23 SPI1_MISO B19 ...

Page 4

... XM_D[7] Y4 XM_D[32] XM_D[8] AA2 XM_D[33] XM_D[9] Y1 XM_D[34] XM_D[10] W4 XM_D[35] XM_D[11] Y2 XM_D[36] XM_D[12] W1 XM_D[37] XM_D[13] V1 XM_D[38] Table 2. D740 Ball Assignment (VDD = 3.3V D21 AC16 AT572D740 4 Ball Name AD25 SPI0_MOSI AE26 SPI0_NSS U3 XM_D[39] V2 XM_D[40] L1 XM_D[41] K3 XM_D[42] L2 XM_D[43] K4 XM_D[44] K1 XM_D[45] K2 XM_D[46] J1 XM_D[47] J2 XM_D[48] ...

Page 5

... AT572D740 AF11 AF19 AF23 A2 C24 ...

Page 6

... ARM_NWEB0 ARM external memory Low Byte Write enable ARM ARM_NWEB1 ARM external memory High Byte Write enable mAgic FPU_HALT ARM Fast IRQ from mAgic “halt” AT572D740 6 Active Type Level Notes in digital serial audio stream bit rate clock ( sampling bit Left + 24 bit right digital serial ...

Page 7

... SPI MST à data input SPI SLV à CS Input bi-02 SPI MST à Output SPI SLV à n.a. out-02 SPI MST à Outputs SPI SLV à clock input bi-03 SPI MST à clock output SPI SLV à data input bi-02 SPI MST à data output AT572D740 7 ...

Page 8

... VDD IO power supply Power VDDI Core power supply Power VDDPLL PLL power supply Ground GND D740 ground reference AT572D740 8 Active Type Level Notes SPI SLV à data output bi-02 SPI MST à data input SPI SLV à CS Input bi-02 SPI MST à Output SPI SLV à ...

Page 9

... Amba ASB MAAR Shared Mux / Demux Memory mAgic DSP core Data Buffer word Double Bank Double Port Data / Program Bus Mux AT572D740 ASB / APB Bridge SPI0 SPI1 USART0 USART1 Data Bus TIMER Watchdog Data Memory PIO (6k+6k bit Double Bank ...

Page 10

... Architectural Overview System management mAgic DSP Processor Core processor AT572D740 10 DIOPSIS 740 (also named D740 high performance dual-core processing platform for audio, communication and beam-forming applications, integrating a floating-point DSP (mAgic DSP) and an ARM7TDMI™ Reduced Instruction Set Computer (RISC). The D740 is optimally suited for floating point applications with a significant need for complex domain computations like FFT and frequency domain phase-shift algorithms, requiring high dynamic range and maximum numerical precision ...

Page 11

... Predicated instruction execution is supported for different groups of instructions: arithmetical instructions, memory write, immediate load, or all of them. The Program Address Generation Unit also allows to perform conditioned and unconditioned branch instructions, loops, call to subroutines and return from sub- routines. AT572D740 mAgic – ARM I/F PARM PARM Memory ...

Page 12

... Internal memories, External memories and DMA AT572D740 12 mAgic has four on-chip memory blocks: the Program Memory, the Data Memory, the Data Buffer, and the dual ported memory shared with the ARM processor. An External Memory Interface multiplexes the Data accesses and the Program accesses to and from the External Memory ...

Page 13

... Most application programs execute in User mode. The non-user modes - known as privileged modes – are entered in order to service interrupts or exceptions access protected resources. Each operating mode has dedicated banked registers for fast exception handling. The FIQ mode has five addi- AT572D740 13 ...

Page 14

... AT572D740 14 tional banked working registers, r8_fiq to r12_fiq, to enhance interrupt processing speed. The ARM7TDMI processor operates in little-endian mode. To speed-up critical routine execution or critical data segment access, the ARM7 is equipped with 32 Kbyte of zero wait states on-chip memory. The ARM system has two buses. The main bus is the ASB (ARM System Bus). The APB (ARM Peripheral Bus) is designed for accesses to on-chip peripherals ...

Page 15

... Figure 3. Armsystem Architecture 7001AS–DPS–03/04 AT572D740 15 ...

Page 16

... Development Tools AT572D740 16 D740 is supported with a complete set of software and hardware development tools. MADE The D740 is supported by a set of development tools integrated into a visual develop- ment environment called MADE (Multicore Application Development Environment). MADE provides the user with an integrated environment for producing applications for both the D740 cores, the ARM7TDMI and the mAgic DSP, by means of a common project management and support for the MARMOS Minimal Bios ...

Page 17

... Mechanical Drawing 7001AS–DPS–03/04 AT572D740 17 ...

Page 18

... AT572D740 18 Table 7. D740 Dimensions (mm) Symbol Min Nom A1 0.50 0.60 ∅ b 0.60 0.75 aaa 0.30 bbb 0.25 ccc 0.35 ddd 0.30 eee 0.15 A 2.12 2.33 Dim “B” 0.44 0.52 e REF 1.27 D/E 34.8 35.0 D1/E1 30.0 f REF 11.0 J/L REF 1.62 Max 0.70 0.90 2.56 0.60 35.2 30.7 7001AS–DPS–03/04 ...

Page 19

... Note: Idd represents worst-case processor operation (for Idd IO particularly) and it is not peak considerable for also for hard applications where all data bits do not toggle every cycle. AT572D740 worst conditions Idd IO (3.3V) mA Idd CORE (1.8V) mA 425 600 155 520 ...

Page 20

... Reliability Data AT572D740 20 The following table summarizes some basic data that can be used in reliability calculations. Table 9. Silicon Block Size Parameters Logic Gates Memories Register File total Device Die Size (pad excluded) Data Unit Data 585 Kgates 10 transistors 18 0.3 M transistors 5.1 45 Unit ...

Page 21

... Ordering Guide Table 10. Ordering Information Part Number Temperature Range AT572D740 0°C - 70°C 7001AS–DPS–03/04 Working Frequency Operating Supplies 100 MHz 3.3V (I/O) & 1.8V (core) AT572D740 Package 352PBGA 21 ...

Page 22

... Fax: (81) 3-3523-7581 Disclaimer: Atmel Corporation makes no warranty for the use of its products, other than those expressly contained in the Company’s standard warranty which is detailed in Atmel’s Terms and Conditions located on the Company’s web site. The Company assumes no responsibility for any errors which may appear in this document, reserves the right to change devices or specifications detailed herein at any time without notice, and does not make any commitment to update the information contained herein ...

Related keywords