r8a66171dd Renesas Electronics Corporation., r8a66171dd Datasheet
r8a66171dd
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r8a66171dd Summary of contents
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... R8A66171DD/ (ADVANCED ASYNCHRONOUS RECEIVER & TRANSMITTER) DESCRIPTION The R8A66171 is an integrated circuit for asynchronous serial data communications used in combina- tion with an 8-bit microprocessor and is produced using the silicon gate CMOS technology. R8A66171 is the succession product of M66230. FEATURES ● Baud rate generator ● ...
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... R8A66171DD/SP FUNCTION The R8A66171 is a UART (Universal Asynchronous Receiver/Transmitter) and is used in the peripheral circuit of a MCU. The R8A66171 receives parallel data, converts into serial format, and then transmits the serial data via the TxD pin. The device also receives data via the RxD pin from external circuits and converts it into parallel format, and sends the parallel data via the data bus ...
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... Note : X="L" or "H" TABLE 1. Access method of the R8A66171 REJ03F269-0100 Rev.1.00 Feb.19.2008 Page I/OR I/ R8A66171DD/SP R8A66171 operation Data bus Receiving data buffer(FIFO) Read receive data Data bus Transmit data buffer(FIFO) Write transmit data Data bus Status register Data bus ...
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... R8A66171DD/SP PIN DESCRIPTIONS Pin Name X1 Clock input X2 Clock output RESET Reset input CS Chip select input Command/Data control C/D input RD Read control input WR Write control input D0~D7 Data bus INT Interrupt output RxD Reception data input TxD Transmission data output P0 Port output P1 Port output ...
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... R8A66171DD/SP DISCRIPTION OF FUNCTION ● Baud rate generator The 8-bit programmable divider (baud rate generator) generates the baud rate for transmit or receive. The division rate is (n+1) with a range of n=0~255. The baud rate is calculated by the following formula: baud rate = prescaler division (2 or 32)・baud rate generator division rate (n+1)・16 The prescaler division rate is set by the D0 bit of command1 ...
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... R8A66171DD/SP Example : Block length=6 DATA DATA DATA DATA Transmit data buffer(FIFO) MCU or DATA DATA Transmit data buffer(FIFO) ● Receive data buffer (FIFO) The receive data buffer (FIFO) consists of 4-bytes. The receive data buffer (FIFO) functions according to the block length. Block length=1~3 When the data of the block length is received and /INT is set to low-level, the interrupt output /INT becomes low-level ...
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... R8A66171DD/SP SUPPLEMENTARY DESCRIPTION FIFO The major purpose is not to interrupt the MCU by each character. The MCU is interrupted when: Transmit data buffer (FIFO) empty Receive data buffer (FIFO) full or packet end The MCU interruption interval is as follows: Approximately 90µs (min) until the FIFO becomes full at 500kbps. ...
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... R8A66171DD/SP ● Error detection (1)Parity error When a parity error occurs, D5 bit of status1 information is set. The data is send to the receive data buffer (FIFO). (2)Framing error When a framing error occurs, D3 bit of the status1 information is set. The data is sent to the receive data buffer (FIFO). ...
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... R8A66171DD/SP PROGRAMMING The command must be loaded first to the R8A66171 by the MCU before data communication. R8A66171 has 6 command registers. Data transfer is possible when commands have been loaded to these command registers after reset. The flowchart of the initial setting is shown in the following diagram. Reset ...
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... R8A66171DD/SP COMMAND-INSTRUCTION FORMAT The commands are decoded by D7 and D6. Command1 Note 1 : Priority is given to parity enable, if parity enable and CRC enable are both "1" (D3, D2=1). Note 2 : TxD output wave is Stop bit (D5) setup value +1 (always). Command2 (Baud rate setting. The second byte when D1 bit of the command1 is set to "1".） ...
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... R8A66171DD/SP Command4 Command5 (Address setting. The second byte when D2 bit of the command4 is set to “1”.) Command5 （ Address setting. The second byte when D2 bit of the command4 bit is set to "1". ） Command6 REJ03F269-0100 Rev ...
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... R8A66171DD/SP STATUS INFORMATION ・Status 1 and 2 cannot address setting from external pin. Discrimination of status used to D7 bit. ・Status 1 and 2 has read mutually. (There are not continuity read of same status.) Status1 0 CRCE Status2 REJ03F269-0100 Rev.1.00 Feb.19.2008 ...
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... R8A66171DD/SP TRANSMISSION FORMAT Transmit format Parity enabled MCU → R8A66171 Assembled data format Start bit ( 1 bit ) Transmitter output TxD mark Start bit condition ( 1 bit ) CRC enabled MCU → R8A66171 After assembly Start bit ( 1 bit ) Transmitter output TxD mark Start bit condition ...
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... R8A66171DD/SP TRANSMISSION FORMAT Receive format Parity enabled Receiver input RxD mark Start bit condition ( 1 bit ) Receive format Start bit ( 1 bit ) R8A66171 → MCU CRC enabled Receiver input Start bit RxD mark ( 1 bit ) condition Block length m+1 Start bit ( 1 bit ) Start bit Block check character ( 8 bits ) ...
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... R8A66171DD/SP ABSOLUTE MAXIMUM RATINGS Symbol Parameter V Supply voltage CC VI Input voltage Output voltage VO Power dissipation Pd Tstg Storage temperature RECOMMENDED OPERATING CONDITIONS Symbol Parameter V Supply voltage CC GND Ground Topr Operating temperature ELECTRICAL CHARACTERISTICS 5.0V version support specifications (Ta=-40~85 Symbol Parameter VIH High-level input voltage ...
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... R8A66171DD/SP TIMING REQUIREMENTS Symbol t (X1) Clock frequency C1 Clock high-level t (X1) WH1 pulse width (Except Wakeup, CRC mode) Clock low-level t (X1) WL1 pulse width t (X1) Clock frequency C2 Clock high-level t (X1) WH2 pulse width Clock low-level t (X1) WL2 pulse width tr(X1) Clock rise time ...
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... R8A66171DD/SP TEST CIRCUIT Input Vcc P.G. DUT 50Ω GND TIMING DIAGRAM Input/output waveform at read data and read status RD 50% t (/R-DQ) PZL D0~D7 50% t (/R-DQ) PZH D0~D7 50% Clock Timing t WL (X1) 90% 50 10% 10 REJ03F269-0100 Rev.1.00 Feb.19.2008 Page Vcc Output Parameter RL=1kΩ tPLH, tPHL ...
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... R8A66171DD/SP Write control cycle (MCU→R8A66171) tsu(A-/W) 50% CS C/D 50% tsu(A-/W) WR 50% D0~D7 INT RTS, P0, P1 Read control cycle (R8A66171→MCU) tsu(A-/R) 50% CS C/D 50% tsu(A-/R) RD 50% D0~D7 REJ03F269-0100 Rev.1.00 Feb.19.2008 Page th(/W-A) 50% 50% th(/W-A) t (/W) W 50% th(/W-DQ) tsu(DQ-/W) 50% 50% Valid data t t (/W-/INT) PLH PHL , 50% t (/W-/RTS,P0,P1) ...
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... R8A66171DD/SP Write data cycle (MCU→R8A66171) tsu(A-/W) 50% CS tsu(A-/W) C/D 50% WR 50% D0~D7 INT Read data cycle (R8A66171→MCU) tsu(A-/R) CS 50% tsu(A-/R) C/D 50% RD 50% D0~D7 INT REJ03F269-0100 Rev.1.00 Feb.19.2008 Page th(/W-A) 50% th(/W-A) 50% t (/W) W 50% tsu(DQ-/W) th(/W-DQ) 50% 50% Valid data t t (/W-/INT) PLH PHL , 50% th(/R-A) 50% th(/R-A) 50% t (/R) W 50% ...
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... R8A66171DD/SP Transmitter control and flag timing (1) Block length=1 C/D WR TXEN DATA1 CTS INT T BEMP X (Status (2) Block length=3 C/D WR DATA1 DATA2 DATA3 TXEN CTS INT T BEMP X (Status DATA1 (3) Block length=5 C/D WR DATA1 DATA3 TXEN DATA2 DATA4 CTS INT T BEMP X (Status DATA1 REJ03F269-0100 Rev ...
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... R8A66171DD/SP Receiver control and flag timing (1) Block length=1 C/D RD RXEN WR INT R BPE X (Status) OE (Status) RxD DATA1 (2) Block length=3 C RXEN INT R BPE X (Status) OE (Status) RxD DATA1 DATA2 DATA3 (3)Block length=5 C RXEN INT R BFULL X (Status) R BPE X (Status) OE (Status) RxD ~ DATA1 DATA4 REJ03F269-0100 Rev.1.00 Feb.19.2008 ...
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... R8A66171DD/SP PACKAGE OUTLINE Product Name R8A66171DD R8A66171SP 24pin SOP All trademarks and registered trademarks are the property of their respective owners. REJ03F269-0100 Rev.1.00 Feb.19.2008 Page Package RENESAS Code 24pin DIP PRDP0024AF-A PRSP0024DF-A Previous Code 24P4X-A 24P2X-B ...
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