r8a66174sp Renesas Electronics Corporation., r8a66174sp Datasheet
r8a66174sp
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r8a66174sp Summary of contents
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... R8A66174SP PARALLEL-IN SERIAL-OUT DATA BUFFER WITH FIFO DESCRIPTION The R8A66174 is a CMOS LSI with 63-byte FIFO (First-In First-Out Memory). The commands 63- bytes data can be stored from 8-bit data bus. The data stored in FIFO can be outputted as serial data by executing command, and when the stored data is outputted all, R8A66174 will output an interrupt request signal ...
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... R8A66174SP BLOCK DIAGRAM DATA BUS SELECTOR COMMAND/ 19 C/D DATA INPUT INPUT CHIP SELECT CS 18 CONTROL INPUT CIRCUIT 1 WR WRITE INPUT CK COMMAND REGISTER Φ CLOCK INPUT 11 DIVIDER INTERRUPT REQUEST INT 16 OUTPUT RESET RESET 17 INPUT FUNCTIONAL DESCRIPTION The information on data bus D0~D7 is loaded as command when C//D=1, and as data when C//D=0 ...
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... R8A66174SP BASIC OPERATION Fig. 1 shows the basic operation flowchart. Data inputs D0~D7 are switched among four commands and 8-bit parallel data by the C//D signal. When C// the command is stored in sync with the rise of /WR. For initiate to work this IC, at first command 1 should be stored. Command 1 sets the division ratio for clock input Φ ...
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... R8A66174SP PIN DESCRIPTION INSTRUCTION SET Four commands can be set by the 8-bit command words from the CPU. Table 2 Command setting Fig. 2 shows the method for determining the command word for the instruction set. When D3~D0 are masked and when masked. ...
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... R8A66174SP When Fig. 2 Instruction set REJ03F0278-0101 Rev.1.01 Oct.06.2008 Page Division ratio setting 1 Set/Reset LATCH and /OE, 1 and cancel /INT 1 When D3 = When Division ratio Φ 1/2 of Φ 1/4 of Φ 1/8 of Φ ...
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... R8A66174SP EXAMPLE OF TIME CHART REJ03F0278-0101 Rev.1.01 Oct.06.2008 Page ...
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... R8A66174SP ABSOLUTE MAXIMUM RATINGS Parameter Symbol Supply voltage Vcc Input voltage V I Output voltage Vo Pd Power dissipation Storage temperature Tstg RECOMMENDED OPERATING CONDITIONS （ Ta=-40~85 Symbol Vcc Supply voltage Supply voltage GND Input voltage V I Output voltage Vo Operating temperature range Topr ELECTRICAL CHARACTERISTICS ■ ...
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... R8A66174SP TIMING REQUIREMENTS (Ta=-40~85 Symbol Parameter Clock pulse width tw(Φ) Write pulse width tw(/W) Reset pulse width tw(/R) t (D-/W) Data setup time before write su t (/W-D) Data hold time after write h Address setup time before write t (A-/W) su Address hold time after write t (/W-A) h Write recovery time ...
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... R8A66174SP TIMING DIAGRAM Instruction set 1~4 Φ (Note 13) C/D, CS INPUTS tsu(A-/W) WR D0~D7 SCLK (Note 14) SDATA (Note 14) OUTPUTS OE, LATCH (Note 15) trec(/INT-/W) INT (Note 15) Note 13 : The timing diagram when division ratio is set (1/2, 1/4, 1/8, 1/16) is regarded as the waveform as divided by Φ. Timing diagram when RESET RESET INPUTS WR OE ...
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... HC373 ROM RAM Φ Φ C RESET R8A66174SP INT SDATA SCLK OE LATCH Interrupt control circuit SQP A SQP R8A66160 ...
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... R8A66174SP PACKAGE OUTLINE Package 20pin SOP All trademarks and registered trademarks are the property of their respective owners. REJ03F0278-0101 Rev.1.01 Oct.06.2008 Page RENESAS Code Previous Code PRSP0020DG-A 20P2X-C ...
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