hcts160ms Intersil Corporation, hcts160ms Datasheet

no-image

hcts160ms

Manufacturer Part Number
hcts160ms
Description
Radiation Hardened Synchronous Counter
Manufacturer
Intersil Corporation
Datasheet
September 1995
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Copyright © Intersil Corporation 1999
Features
• 3 Micron Radiation Hardened SOS CMOS
• Total Dose 200K RAD (Si)
• SEP Effective LET No Upsets: >100 MEV-cm
• Single Event Upset (SEU) Immunity < 2 x 10
• Dose Rate Survivability: >1 x 10
• Dose Rate Upset: >10
• Latch-Up Free Under Any Conditions
• Fanout (Over Temperature Range)
• Military Temperature Range: -55
• Significant Power Reduction Compared to LSTTL ICs
• DC Operating Voltage Range: 4.5V to 5.5V
• LSTTL Input Compatibility
• Input Current Levels Ii
Description
The Intersil HCTS160MS is a Radiation Hardened high speed
presettable BCD decade synchronous counter that features an
asynchronous reset and look-ahead carry logic. Counting and
parallel presetting are accomplished synchronously with the low-
to-high transition of the clock. A low level on the synchronous
parallel enable input, SPE, disables counting and allows data at
the preset inputs, P0 - P3, to be loaded into the counter. The
counter is reset by a low on the master reset input, MR. Two count
enables, PE and TE are provided for n-bit cascading. TE also
controls the terminal count output, TC. The terminal count output
indicates a maximum count for one clock pulse and is used to
enable the next cascaded stage to count.
The HCTS160MS utilizes advanced CMOS/SOS technology to
achieve high-speed operation. This device is a member of
radiation hardened, high-speed, CMOS/SOS Logic Family.
The HCTS160MS is supplied in a 16 lead Ceramic flatpack
(K suffix) or a SBDIP Package (D suffix).
Ordering Information
HCTS160DMSR
HCTS160KMSR
HCTS160D/Sample
HCTS160K/Sample
HCTS160HMSR
(Typ)
-Standard Outputs 10 LSTTL Loads
-VIL = 0.8V Max
-VIH = VCC/2 Min
PART NUMBER
10
RAD (Si)/s 20ns Pulse
5 A @ VOL, VOH
TEMPERATURE RANGE
12
o
C to +125
-55
-55
RAD (Si)/s
o
o
C to +125
C to +125
+25
+25
+25
o
o
o
o
C
C
C
-9
C
2
/mg
Errors/Bit-Day
o
o
C
C
560
Intersil Class S Equivalent
Intersil Class S Equivalent
Sample
Sample
Die
HCTS160MS
SCREENING LEVEL
Pinouts
GND
MR
CP
PE
P0
P1
P2
P3
FLATPACK PACKAGE (FLATPACK)
16 LEAD CERAMIC DUAL-IN-LINE
16 LEAD CERAMIC METAL SEAL
METAL SEAL PACKAGE (SBDIP)
GND
MR
CP
MIL-STD-1835 CDFP4-F16
PE
P0
P1
P2
P3
MIL-STD-1835 CDIP2-T16
1
2
3
4
5
6
7
8
Synchronous Counter
1
2
3
4
5
6
7
8
TOP VIEW
TOP VIEW
Radiation Hardened
16 Lead SBDIP
16 Lead Ceramic Flatpack
16 Lead SBDIP
16 Lead Ceramic Flatpack
Die
Spec Number
16
15
14
13
12
11
10
9
File Number
PACKAGE
16
15
14
13
12
11
10
9
VCC
TC
Q0
Q1
Q2
Q3
TE
SPE
518611
2484.2
VCC
TC
Q0
Q1
Q2
Q3
TE
SPE

Related parts for hcts160ms

hcts160ms Summary of contents

Page 1

... The HCTS160MS utilizes advanced CMOS/SOS technology to achieve high-speed operation. This device is a member of radiation hardened, high-speed, CMOS/SOS Logic Family. The HCTS160MS is supplied lead Ceramic flatpack (K suffi SBDIP Package (D suffix). Ordering Information PART NUMBER ...

Page 2

... The TC output is HIGH when TE is HIGH and the counter is at terminal count (HHHH for 161 and HLLH for 160) 2. The HIGH-to-LOW transition the 54/74161 and 54/74160 should only occur while CP is high for conventional operation 3. The LOW-to-HIGH transition of SPE on the 54/74161 and 54/74160 should only occur while CP is high for conventional operation HCTS160MS P1 4 ...

Page 3

... VCC = 4.5V, VIH = 2.25V, Functional Test VIL = 0.8V (Note 2) NOTES: 1. All voltages referenced to device GND. 2. For functional tests, VO 4.0V is recognized as a logic “1”, and VO Specifications HCTS160MS Reliability Information Thermal Resistance SBDIP Package 10mA Ceramic Flatpack Package . . . . . . . . . . . 25mA Maximum Package Power Dissipation at +125 SBDIP Package ...

Page 4

... The parameters listed in Table 3 are controlled via design or process parameters. Min and Max Limits are guaranteed but not directly tested. These parameters are characterized upon initial design release and upon design changes which affect these characteristics. Specifications HCTS160MS GROUP (NOTES 1, 2) ...

Page 5

... AC measurements assume RL = 500 , CL = 50pF, Input 3ns, VIL = GND, VIH = 3V. 3. For functional tests VO 4.0V is recognized as a logic “1”, and VO TABLE 5. BURN-IN AND OPERATING LIFE TEST, DELTA PARAMETERS (+25 PARAMETER ICC IOL/IOH Specifications HCTS160MS (NOTES 1, 2) CONDITIONS TEMPERATURE 0.5V is recognized as a logic “0”. GROUP B SUBGROUP ...

Page 6

... Each pin except VCC and GND will have a resistor of 1K OPEN NOTE: Each pin except VCC and GND will have a resistor of 47K Group E, Subgroup 2, sample size is 4 dice/wafer 0 failures. Specifications HCTS160MS TABLE 6. APPLICABLE SUBGROUPS METHOD GROUP A SUBGROUPS 100%/5004 ...

Page 7

... Variables Data (All Delta operations). Data is identified by serial number. Data header includes lot number and date of test. • The Certificate of Conformance is a part of the shipping invoice and is not part of the Data Book. The Certificate of Conformance is signed by an authorized Quality Representative. HCTS160MS 100% Interim Electrical Test 1 (T1) 100% Delta Calculation (T0-T1) 100% Static Burn-In 2, Condition hrs ...

Page 8

... For information regarding Intersil Corporation and its products, see web site http://www.intersil.com Sales Office Headquarters NORTH AMERICA Intersil Corporation P. O. Box 883, Mail Stop 53-204 Melbourne, FL 32902 TEL: (321) 724-7000 FAX: (321) 724-7240 HCTS160MS AC Load Circuit TPHL TTHL 80% 20% UNITS V ...

Page 9

... Metallization Mask Layout P0 (3) P1 (4) P2 (5) P3 (6) PE (7) NOTE: The die diagram is a generic plot from a similar HCS device intended to indicate approximate die size and bond pad location. The mask series for the HCTS160 is TA14445A. HCTS160MS HCTS160MS CD MR VCC (2) (1) (16) (8) (9) ...

Related keywords