ep610i-15 Altera Corporation, ep610i-15 Datasheet
ep610i-15
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ep610i-15 Summary of contents
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... Cadence, Exemplar Logic, Mentor Graphics, OrCAD, Synopsys, Synplicity, and VeriBest Table 1. Classic Device Features Feature Usable gates Macrocells Maximum user I/O pins t (ns (MHz) CNT EPLD Family ® MAX+PLUS EP610 EP910 EP610I EP910I 300 450 100 76.9 Classic Data Sheet ® II EP1810 900 ...
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... EDA tools. The MAX+PLUS II software runs on Windows-based PCs, as well as Sun SPARCstation, HP 9000 Series 700/800, and IBM RISC System/6000 workstations. These devices also contain on-board logic test circuitry to allow verification of function and AC specifications during standard production flow. Altera Corporation ...
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... Functional Description Altera Corporation For more information, see the Development System & Software Data The Classic architecture includes the following elements: Macrocells Programmable registers Output enable/clock select Feedback select Macrocells Classic macrocells, shown in both sequential and combinatorial logic operation. Eight product terms form a programmable-AND array that feeds an OR gate for combinatorial logic implementation ...
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... This mode allows registers to be individually clocked by any signal on the AND array. With both true and complement signals in the AND array, the register can be configured to trigger on a rising or falling edge. This product-term-controlled clock configuration also supports gated clock structures. Altera Corporation ...
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... Figure 3. Classic Feedback Multiplexer Configurations Global Feedback Multiplexer Q Global I/O EP610 EP610I EP910 EP910I Altera Corporation Figure 2. Classic Output Enable/Clock Select AND Array OE = Product Term CLK = Global AND Array ...
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... Classic EPLD Family Data Sheet Design Security Timing Model 750 EP610, EP610I, EP910, and EP910I devices have a global feedback configuration; either the macrocell output (Q) or the I/O pin input (I/O) can feed back to the AND array so that it is accessible to all other macrocells. ...
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... Altera Corporation Timing information can be derived from the timing model and parameters for a particular device. External timing parameters represent pin-to-pin timing delays, and can be calculated from the sum of internal parameters. Figure 5 shows the internal timing relationship for internal and external delay parameters. ...
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... IN t LAD t CLR Global Clock Mode ICS Array Clock Mode ACH ASU AH Output Mode LAD LAD ACL High-Impedance Tri-State Altera Corporation ...
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... Option Generic Testing Device Programming Altera Corporation Many Classic devices contain a programmable Turbo Bit control the automatic power-down feature that enables the low-standby- power mode. When the Turbo Bit option is turned on, the low-standby- power mode is disabled. All AC values are tested with the Turbo Bit option turned on ...
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Notes: ...
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... Pipelined data rates 125 MHz Programmable I/O architecture with inputs or 16 outputs and 2 clock pins EP610 and EP610I devices are pin-, function-, and programming file-compatible Programmable clock option for independent clocking of all registers Macrocells individually programmable JK flipflops, or ...
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... Each macrocell can access signals Macrocell 1 Macrocell 2 Macrocell 3 Macrocell 4 Macrocell 5 Macrocell 6 Macrocell 7 Macrocell 8 ) versus frequency of EP610 CC Turbo Non-Turbo 1 kHz 10 kHz 100 kHz 1 MHz 10 MHz 80 MHz Frequency INPUT (27) 23 CLK2 (16) 13 (26) 22 (25) 21 (24) 20 (23) 19 (22) 18 (21) 17 (20) 16 (18) 15 INPUT (17) 14 Altera Corporation ...
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... Figure 10. Output Drive Characteristics of EP610 Devices Drive characteristics may exceed shown curves. EP610-15 & EP610-20 EPLDs 200 150 Typical I CC Output 100 Current (mA 0.45 V Output Voltage (V) O EP610I EPLDs 100 80 60 Typical I CC Output Current (mA Output Voltage (V) O Altera Corporation Figure 10 shows the typical output drive characteristics of EP610 devices. EP610-25, EP610-30 & ...
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... Classic EPLD Family Data Sheet Operating Conditions Table 2. EP610 & EP610I Device Absolute Maximum Ratings Symbol Parameter V Supply voltage input voltage ground current MAX output current, per pin OUT T Storage temperature STG T Ambient temperature AMB T Junction temperature J Table 3. EP610 & ...
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... Table 5. EP610 & EP610I Device Capacitance Symbol Parameter C Input pin capacitance IN C I/O pin capacitance I/O C CLK1 pin capacitance CLK1 C CLK2 pin capacitance CLK2 Table 6. EP610 Device I Supply Current CC Symbol Parameter I V supply current CC1 CC (non-Turbo, standby supply current CC2 CC (non-Turbo, active) ...
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... When the Turbo Bit option is not set (non-Turbo mode), EP610 devices enter standby mode if no logic transitions occur for 100 ns after the last transition. When the Turbo Bit option is not set, EP610I devices enter standby mode if no logic transitions occur for 75 ns after the last transition. ...
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... Logic array delay LAD t Output buffer and pad delay OD t Output buffer enable delay ZX t Output buffer disable delay XZ Altera Corporation Tables 8 and 9 show the timing parameters for EP610-15 and EP610-20 devices. Conditions ( ...
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... Min Max Min Max Min Max ( (5) 47.6 21.0 0.0 10.0 10.0 (6) 40.0 8.0 12.0 10.0 10.0 ( 1.0 (6) 40.0 EP610-15 EP610-20 Min Max Min Max 5.0 4.0 6.0 2.0 1.0 6.0 Notes (1), (2) EP610-30 EP610-35 Non-Turbo 25.0 30.0 35.0 27.0 32.0 37.0 25.0 30.0 35.0 25.0 30.0 35.0 27.0 32.0 37.0 41.7 37.0 24.0 27.0 0.0 0.0 11.0 12.0 11.0 12.0 15.0 17.0 20.0 25.0 30.0 35.0 33.3 28.6 8.0 8.0 12.0 12.0 11.0 12.0 11.0 12.0 1.0 1.0 27.0 32.0 37.0 25.0 30.0 35.0 33.3 28.6 Altera Corporation Unit 4.0 ns 7.0 ns 11.0 ns 4.0 ns 1.0 ns 11.0 ns Unit Adder (3) 30.0 ns 30.0 ns 30.0 ns 30.0 ns 30.0 ns 0.0 MHz 30.0 ns 0.0 ns 0.0 ns 0.0 ns 0.0 ns 0.0 ns 0.0 MHz 30.0 ns 0.0 ns 0 30.0 ns 0.0 ns 0.0 MHz ...
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... MAX (6) Measured with a device programmed as a 16-bit counter. (7) Sample-tested only. This parameter is a guideline based on extensive device characterization. This parameter applies for both global and array clocking. Altera Corporation Condition EP610-25 Min ...
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... ACO1 t Array clock minimum period ACNT f Maximum internal array clock ACNT frequency 764 Tables 12 and 13 show the timing parameters for EP610I devices. Notes (1), Conditions EP610I-10 EP610I-12 EP610I-15 Non-Turbo Min Max Min Max Min Max ( (5) 125.0 7.0 0.0 5.0 5.0 (6) 100.0 1.5 5 ...
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... Sample-tested only. This parameter is a guideline based on extensive device characterization. This parameter applies for both global and array clocking. Altera Corporation Conditions Table 3 on page 758. Classic EPLD Family Data Sheet EP610I-10 EP610I-12 EP610I-15 Min Max Min Max Min 1.5 4.0 0.0 0.0 5.5 6.0 3 ...
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... Features Altera Corporation High-performance, 24-macrocell Classic EPLD – Combinatorial speeds with t – Counter frequencies 76.9 MHz – Pipelined data rates 125 MHz Programmable I/O architecture with inputs or 24 outputs EP910 and EP910I devices are pin-, function-, and programming file- compatible ...
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... Macrocell 1 (38) Macrocell 2 (37) Macrocell 3 (36) Macrocell 4 (35) Macrocell 5 (34) Macrocell 6 Macrocell 7 (33) Macrocell 8 (32) Macrocell 9 (31) Macrocell 10 (30) Macrocell 11 (29) Macrocell 12 (28) INPUT INPUT INPUT Altera Corporation 39 (43) (42 (41) (24 (27) 24 (26) 23 (25) ...
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... Drive characteristics may exceed shown curves. EP910 EPLDs Typical I O Output 30 Current (mA 0. Altera Corporation Figure 13 shows the typical supply current (I EP910 devices. Figure 13. I vs. Frequency of EP910 Devices CC 100 10 Typical I CC Active (mA) 1.0 0.1 Figure 14 shows the typical output drive characteristics of EP910 devices. EP910I EPLDs ...
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... EP910 EP910I Max Min Max 4.75 5. 0.3 –0 0 100 (50) 500 100 (50) 500 Min Max 2 0.3 CC –0.3 0.8 2.4 3.84 0.45 –10 10 –10 10 Altera Corporation Unit ° C ° C ° C ° C Unit ° C ° Unit µA µA ...
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... When the Turbo Bit option is not set (non-Turbo mode), an EP910 device will enter standby mode if no logic transitions occur for 100 ns after the last transition, and an EP910I device will enter standby mode if no logic transitions occur for 75 ns after the last transition. (11) Measured with a device programmed as a 24-bit counter. Altera Corporation Note (6) Conditions ...
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... Min Max Min Max Min Max 30 33 30 33.0 (5) 41.7 24.0 0.0 12.0 12 (6) 30.0 (6) 33.3 10.0 15.0 15.0 15 (7) 1 33.0 30.0 (6) 33.3 EP910-35 EP910-40 Non- Turbo Adder 35.0 40.0 30.0 38.0 43.0 30.0 35.0 40.0 30.0 35.0 40.0 30.0 38.0 43.0 30.0 37.0 32.3 0.0 27.0 31.0 30.0 0.0 0.0 0.0 13.0 15.0 0.0 13.0 15.0 0.0 21.0 24.0 0.0 35.0 40.0 0.0 28.6 25.0 0.0 10.0 10.0 30.0 15.0 15.0 0.0 16.0 17.0 0.0 16.0 17.0 0.0 1.0 1.0 38.0 43.0 30.0 35.0 40.0 0.0 28.6 25.0 0.0 Altera Corporation Unit ( MHz MHz MHz ...
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... MAX (6) Measured with a device programmed as a 24-bit counter. (7) Sample-tested only. This parameter is a guideline based on extensive device characterization and applies for both global and array clocking. Altera Corporation Condition Table 15 on page 770. ...
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... Conditions EP910I-12 EP910I-15 EP910I-25 Non-Turbo Min Max Min Max Min Max 15.0 ( 15.0 (5) 125.0 8.0 0.0 5.0 5.0 8 13.0 (6) 76.9 3.0 6.0 6.0 6 1.0 ( 16.0 13.0 (6) 76.9 Adder (3) 15.0 25.0 40.0 15.0 25.0 40.0 18.0 28.0 40.0 18.0 28.0 40.0 18.0 28.0 40.0 100.0 62.5 0.0 11.0 16.0 40.0 0.0 0.0 0.0 6.0 10.0 0.0 6.0 10.0 0.0 9.0 14.0 0.0 15.0 25.0 40.0 66.6 40.0 0.0 4.0 8.0 40.0 7.0 8.0 7.5 12.5 7.5 12.5 1.0 1.0 18.0 22.0 40.0 15.0 25.0 40.0 66.6 40.0 Altera Corporation Unit MHz MHz MHz ...
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... MAX (6) Measured with the device programmed as a 24-bit counter. (7) Sample-tested only. This parameter is a guideline based on extensive device characterization and applies for both global and array clocking. Altera Corporation Condition Table 15 on page 770. ...
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... 68-Pin PGA EP1810 Altera Corporation High-performance, 48-macrocell Classic EPLD – Combinatorial speeds with t – Counter frequencies MHz – Pipelined data rates 62.5 MHz Programmable I/O architecture with inputs or 48 outputs Programmable clock option for independent clocking of all registers ...
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... EP1810 devices also have four dedicated inputs (one in each quadrant) that can be used as quadrant clock inputs. If the dedicated input is used as a clock pin, the input feeds the clock input of all registers in that particular quadrant. Figure 16). EP1810 devices are divided of this data sheet for more Altera Corporation ...
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... Macrocell Macrocell 20 31 (H10) Macrocell Macrocell 22 33 (G10) Macrocell Macrocell 24 Altera Corporation Classic EPLD Family Data Sheet Macrocell 48 Macrocell 47 Macrocell 46 Macrocell 45 Macrocell 44 Macrocell 43 Macrocell 42 Macrocell 41 Macrocell 40 Macrocell 39 Macrocell 38 Macrocell 37 Global Bus Macrocell 36 Macrocell 35 Macrocell 34 ...
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... Typical 5 Output Current (mA Output Voltage (V) ) versus frequency for 5 kHz 100 kHz 1 MHz 10 MHz Frequency Output Voltage (V) O Altera Corporation 60 MHz 5 ...
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... V Low-level output voltage OL I I/O pin leakage current of dedicated I input pins I Tri-state output leakage current OZ Altera Corporation Tables 23 through 27 provide information on absolute maximum ratings, recommended operating conditions, operating conditions, and capacitance for EP1810 devices. Conditions With respect to ground With respect to ground No bias ...
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... Table 24 on page 781. Min Max 160 Speed Min Typ Max Grade -20, -25 50 150 -35, -45 35 150 -20, -25 20 -35, - (40) -20, -25 180 225 (250) -35, -45 100 180 (240) parameter refers to low-level TTL OL Altera Corporation Unit Unit µA µ ...
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... Register hold time H t Array clock delay IC t Global clock delay ICS t Feedback delay FD t Register clear time CLR Altera Corporation Tables 28 through 31 show the timing parameters for EP1810-20, EP1810-25, EP1810-35, and EP1810-45 devices. Conditions (3) ( ...
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... 35 (4) 1.0 (3) 35.0 (3) 28.6 (5) 40 EP1810-35 EP1810-45 Non-Turbo Conditions Min Max Min Max 7.0 5 (6) 9.0 10.0 15.0 19.0 4.0 6.0 24.0 Unit Adder (2) 45.0 30.0 ns 50.0 30.0 ns 30.0 30.0 ns 0.0 0.0 ns 15.0 0.0 ns 15.0 0.0 ns 25.0 0.0 ns 45.0 0.0 ns 22.2 0.0 MHz 11.0 30.0 ns 18.0 0.0 ns 45.0 30.0 ns 1.0 ns 45.0 0.0 ns 22.2 0.0 ns 33.3 0.0 MHz Unit Adder (2) 6.0 0.0 ns 5.0 0.0 ns 28.0 30.0 ns 11.0 0.0 ns 11.0 0.0 ns 11.0 0.0 ns 10.0 0.0 ns 18.0 0.0 ns 28.0 30.0 ns 8.0 0.0 ns 7.0 –30.0 ns 32.0 30.0 ns Altera Corporation ...
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... The f values represent the highest frequency for pipelined data. MAX (6) Sample-tested only for an output change of 500 mV. Pin-Out Information Altera Corporation Table 24 on page 781. Table 32 provides pin-out information for EP1810 devices in 68-pin PGA packages. Table 32. EP1810 PGA Pin-Outs Pin Function ...
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Notes: ...