w49f020 ETC-unknow, w49f020 Datasheet
w49f020
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w49f020 Summary of contents
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... The W49F020 is a 2-megabit, 5-volt only CMOS flash memory organized as 256K can be programmed and erased in-system with a standard 5V power supply. A 12-volt V required. The unique cell architecture of the W49F020 results in fast program/erase operations with extremely low current consumption (compared to other comparable 5-volt flash memory products). The device can also be programmed and erased using standard EPROM programmers ...
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... WE DQ2 23 DQ1 22 DQ0 GND Preliminary W49F020 W49F020 OUTPUT CONTROL BUFFER MAIM MEMORY 248K BYTES DECODER BOOT BLOCK 8K BYTES PIN NAME Address Inputs Data Inputs/Outputs Chip Enable Output Enable Write Enable Power Supply DD Ground No Connection DQ0 ...
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... FUNCTIONAL DESCRIPTION Read Mode The read operation of the W49F020 is controlled by CE and OE , both of which have to be low for the host to obtain data from the outputs used for device selection. When CE is high, the chip is de-selected and only standby power will be consumed the output control and is used to gate data from the output pins ...
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... Write Status Detection 7 The W49F020 features a data polling function which used to indicate the end of a program or erase cycle. When the W49F020 is in the internal program or erase cycle, any attemption to read DQ last word loaded will receive the complement of the true data. Once the program or erase cycle is completed, DQ will show the true data ...
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... IN OUT 5555 AA 2AAA 55 5555 80 5555 AA 2AAA 55 5555 A0 5555 AA 2AAA 55 5555 80 5555 AA 2AAA 55 5555 90 5555 AA 2AAA 55 5555 F0 XXXX Preliminary W49F020 DQ. Dout Din High Z High Z/D OUT High Z/D OUT High Z Manufacturer Code DA (Hex Device Code 8C (Hex Addr. Data Addr. Data Addr. Data 5555 AA ...
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... Address Format: A14 A0 (Hex) ADDRESS 5555H 2AAAH 5555H Programmed-Address Byte Program Command Flow Load data AA to address 5555 Load data 55 to address 2AAA Load data A0 to address 5555 Load data Din to programmed- address Pause 50 S Exit - 6 - Preliminary W49F020 DATA AAH 55H A0H Programmed-Data ...
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... BYTE SEQUENCE 1 Write 2 Write 3 Write 4 Write 5 Write 6 Write Chip Erase Acquisition Flow Notes for chip erase: Data Format: DQ7 DQ0 (Hex) Address Format: A14 A0 (Hex) Preliminary W49F020 ADDRESS 5555H 2AAAH 5555H 5555H 2AAAH 5555H Load data AA to address 5555 Load data 55 ...
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... Read address = 00000 data = DA (2) Read address = 00001 data =8C (4) Read address = 00002 data in DQ0 = "1"/"0" ; device code is read for Preliminary W49F020 SOFTWARE PRODUCT DETECTION EXIT (7) ADDRESS DATA 5555H AAH 2AAAH 55H 5555H F0H Pause 10 S Product ...
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... Load data AA to address 5555 Load data 55 to address 2AAA Load data 80 to address 5555 Load data AA to address 5555 Load data 55 to address 2AAA Load data 40 to address 5555 Pause 1 Sec. Exit - 9 - Preliminary W49F020 Publication Release Date: October 1999 Revision A1 ...
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... DQs open IH Other inputs = -0.3V, all DQs open DD Other inputs = V -0.3V/GND GND GND to V OUT 2 -0 Preliminary W49F020 RATING UNIT -0 +70 -65 to +150 -0 +1 +1.0 DD -0.5 to 12.5 LIMITS MIN. TYP. MAX 100 - - 10 - ...
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... TTL Gate and C C +5V D OUT 30 pF for 70nS 100 pF for 90nS (Including Jig and Scope) Output 1.5V 1.5V Test Point Test Point - 11 - Preliminary W49F020 TYPICAL UNIT 100 5 mS MAX. UNIT 12 6 CONDITIONS = 100 pF for 90nS for 70nS L 1.8K 1.3K Publication Release Date: October 1999 ...
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... WE High Width Data Setup Time Data Hold Time Byte programming Time Erase Cycle Time Note: All AC timing signals observe the following guidelines for determining setup and hold times: (a) High level signal's reference level is V Preliminary W49F020 SYM. W49F020-70 MIN. MAX ...
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... OE to Data Polling Output Delay CE to Data Polling Output Delay OE to Toggle Bit Output Delay CE to Toggle Bit Output Delay TIMING WAVEFORMS Read Cycle Timing Diagram Address A17 High-Z DQ7-0 Preliminary W49F020 SYM. W49F020-70 MIN. MAX OEP CEP T ...
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... Timing Waveforms, continued Controlled Command Write Cycle Timing Diagram WE Address A17 DQ7-0 Controlled Command Write Cycle Timing Diagram CE Address A17 DQ7-0 Preliminary W49F020 OES Data Valid OES T DS High Z Data Valid ...
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... CE OE DQ7 Byte Program Cycle 2AAA 5555 Address 5555 WPH T WP Byte 1 Byte 0 Byte 2 T CEP T OEH T OEP Preliminary W49F020 Data- Internal Write Start Byte 3 T OES X X Publication Release Date: October 1999 Revision A1 ...
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... Address A17-0 DQ7 OEH Six byte code for Boot Block Lockout Feature Enable 5555 5555 2AAA 5555 2AAA XX55 XX80 XXAA XXAA XX55 WPH SB0 SB2 SB3 SB1 SB4 - 16 - Preliminary W49F020 T OES 5555 XX40 T EC SB5 ...
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... DQ7 Six-byte code for 5V-only software chip erase 5555 5555 2AAA 5555 2AAA XX55 XX80 XXAA XXAA XX55 WPH SB0 SB2 SB3 SB1 SB4 - 17 - Preliminary W49F020 5555 XX10 T EC Internal Erase starts SB5 Publication Release Date: October 1999 Revision A1 ...
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... PLCC 50 100 (CMOS) 32-pin DIP 50 100 (CMOS) 32-pin DIP 50 100 (CMOS) 32-pin TSOP ( 100 (CMOS) 32-pin TSOP ( 100 (CMOS) 32-pin PLCC 50 100 (CMOS) 32-pin PLCC - 18 - Preliminary W49F020 PACKAGE CYCLE 20 mm) 20 mm) 20 mm 10K ...
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... Base Plane Seating Plane Preliminary W49F020 Dimension in inches Dimension in mm Symbol Min. Nom. Max. Min. Nom. Max. A 0.210 5.33 A 0.010 0. 0.150 0.155 0.160 3.81 3.94 4. 0.016 0.018 0.41 0.46 0.56 0.022 B 0 ...
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... Package Dimensions, continued 32-pin TSOP 0.10(0.004 Preliminary W49F020 Dimension in Inches Dimension in mm Symbol Min. Nom. Min. Nom. Max. Max 0.047 1. 0.002 0.006 0.05 0. 0.95 0.037 0.039 0.041 1.00 1. 0.007 0.008 0.17 0.20 0.23 0.009 c 0 ...
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... Taipei Office 11F, No. 115, Sec. 3, Min-Sheng East Rd., Taipei, Taiwan TEL: 886-2-27190505 FAX: 886-2-27197502 Note: All data and specifications are subject to change without notice. Preliminary W49F020 PAGE - Initial Issued Winbond Electronics (H.K.) Ltd. Winbond Electronics North America Corp. Winbond Memory Lab. ...