w49f020 ETC-unknow, w49f020 Datasheet - Page 4

• Manufacturer Part Number: w49f020
• Manufacturer: ETC-unknow

T
can be used to detect end of program cycle.
Hardware Data Protection
The integrity of the data stored in the W49F020 is also hardware protected in the following ways:
(1) Noise/Glitch Protection: A WE pulse with less than 15 nS in duration will not initiate a write cycle.
(2) V
(3) Write Inhibit Mode: Forcing OE low, CE high, or WE high will inhibit the write operation. This
(4) V
Data Polling (DQ
The W49F020 features a data polling function which used to indicate the end of a program or erase
cycle. When the W49F020 is in the internal program or erase cycle, any attemption to read DQ
last word loaded will receive the complement of the true data. Once the program or erase cycle is
completed, DQ
become logical "1" or true data when the erase cycle has been completed.
Toggle Bit (DQ
In addition to data polling, the W49F020 provides another method for determining the end of a program
cycle. During the internal program or erase cycle, any consecutive attempts to read DQ
alternating 0's and 1's. When the program or erase cycle is completed, this toggling between 0's and 1's
will stop. The device is then ready for the next operation.
Product Identification
The product ID operation outputs the manufacturer code and device code. Programming equipment
automatically matches the device with its proper erase and programming algorithms.
The manufacturer and device codes can be accessed by software or hardware operation. In software
access mode, a three-word (or JEDEC 3-word) command sequence can be used to access the product
ID. A read from address 0000H outputs the manufacturer code DA(hex); and a read from address
0001H outputs the device code 8C(hex) for W49F020. The product ID operation can be terminated by a
three-word command sequence or an alternated one-word command sequence (see Command
Definition table).
In the hardware access mode, access to the product ID will be activated by forcing CE and OE low,
WE high, and raising A9 to 12 volts.
BP
) when completing programming and return to normal read mode. Data polling and/or Toggle Bits
2.5V typical.
prevents inadvertent writes during power-up or power-down periods.
5 mS before any write (erase/program) operation.
DD
DD
power-on delay: When V
Power Up/Down Detection: The programming operation is inhibited when V
7
will show the true data. Note that DQ
6
)- Write Status Detection
7
)- Write Status Detection
DD
has reached its sense level, the device will automatically time-out
- 4 -
7
will show logical "0" during the erase cycle, and
Preliminary W49F020
DD
is less than
6
will produce
7
of the