w39f010 Winbond Electronics Corp America, w39f010 Datasheet
w39f010
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w39f010 Summary of contents
Page 1
... Device Bus Operations ................................................................................................. 12 7.2 Command Definitions ................................................................................................... 12 7.3 Embedded Programming Algorithm ............................................................................. 14 7.4 Embedded Erase Algorithm.......................................................................................... 15 7.5 Embedded #Data Polling Algorithm.............................................................................. 16 7.6 Boot Block Lockout Enable Flow Chart ........................................................................ 17 7.7 Software Product Identification and Boot Block Lockout Detection Flow Chart........... 18 128K u 8 CMOS FLASH MEMORY Publication Release Date: December 26, 2005 - 1 - W39F010 Revision A4 ...
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... Page Erase Timing Diagram ........................................................................................ 25 10.6 #DATA Polling Timing Diagram .................................................................................... 25 10.7 Toggle Bit Timing Diagram ........................................................................................... 26 11. ORDERING INFORMATION .................................................................................................... 27 12. HOW TO READ THE TOP MARKING...................................................................................... 28 13. PACKAGE DIMENSIONS ......................................................................................................... 29 13.1 32-pin P-DIP ................................................................................................................. 29 13.2 32-pin TSOP ( mm)............................................................................................. 30 13.3 32-pin PLCC ................................................................................................................. 31 13.4 32-pin STSOP ( mm) .......................................................................................... 31 14. VERSION HISTORY ................................................................................................................. W39F010 ...
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... Software method: Toggle bit/Data polling O TTL compatible I/O O JEDEC standard byte-wide pinouts O Available packages: 32-pin 600 mil DIP, 32-pin PLCC, 32- pin STSOP ( mm) and 32- pin TSOP is not required. The unique cell architecture of the W39F010 PP Publication Release Date: December 26, 2005 - 3 - W39F010 Revision A4 ...
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... 32-pin TSOP Publication Release Date: December 26, 2005 - 4 - W39F010 V DD #WE NC A14 A13 A8 A9 A11 #OE A10 #CE DQ7 DQ6 DQ5 DQ4 DQ3 A14 A13 A8 A9 A11 #OE A10 #CE DQ7 #OE 32 A10 ...
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... VDD Detect Timer Erase Voltage Generator Program Voltage Generator Chip Enable Output Enable Logic A Y-Decode X-decode Publication Release Date: December 26, 2005 - 5 - W39F010 Input / output Buffers Data latch Y-MUX / SENSING ARRAY Revision A4 ...
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... PIN DESCRIPTION SYMBOL A0 A16 DQ0 DQ7 #CE #OE # PIN NAME Address Inputs Data Inputs/Outputs Chip Enable Output Enable Write Enable Power Supply Ground No Connections - 6 - W39F010 ...
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... Read Mode The read operation of the W39F010 is controlled by #CE and #OE, both of which have to be low for the host to obtain data from the outputs. #CE is used for device selection. When #CE is high, the chip is de-selected and only standby power will be consumed. #OE is the output control and is used to gate data from the output pins ...
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... DC Characteristics section for voltages). The write and read operations are DD inhibited when V is less than 2.0V typical. The W39F010 ignores all write and read operations until DD V > 2,0V. The user must ensure that the control pins are in the correct logic state when prevent unintentional writes ...
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... The operation is initiated by writing the auto-select command sequence into the command register. Following the command write, a read cycle from address XX00H retrieves the manufacture code of DAH. A read cycle from address XX01H returns the device code (W39F010 = A1). To terminate the operation necessary to write the auto-select exit command sequence into the register ...
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... Write Operation Status 6.5.1 DQ7: Data Polling The W39F010 device features Data Polling as a method to indicate to the host that the embedded algorithms are in progress or completed. During the Embedded Program Algorithm, an attempt to read the device will produce the complement of the data last written to DQ7. Upon completion of the Embedded Program Algorithm, an attempt to read the device will produce the true data last written to DQ7. During the Embedded Erase Algorithm, an attempt to read the device will produce a " ...
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... Erase Algorithm, or page erase time-out (see "Command Definitions"). 6.5.2 DQ6: Toggle Bit The W39F010 also features the "Toggle Bit" method to indicate to the host system that the embedded algorithms are in progress or completed. During an Embedded Program or Erase Algorithm cycle, successive attempts to read (#OE toggling) data from the device at any address will result in DQ6 toggling between one and zero ...
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... D OUT 2AAA 55 5555 80 5555 AA 2AAA 55 5555 80 5555 AA 2AAA 55 5555 A0 A 2AAA 55 5555 80 5555 AA 2AAA 55 5555 80 5555 AA 2AAA 55 5555 90 2AAA 55 5555 W39F010 PIN DQ0 DQ7 V Dout IH V Din IL X High Z Dout X High Z/ Dout V High High Z IH Addr. Data Addr. Data ...
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... PA = 08XXXh for Page 07XXXh for Page 06XXXh for Page 05XXXh for Page 04XXXh for Page 03XXXh for Page 02XXXh for Page 01XXXh for Page 00XXXh for Page 0 Publication Release Date: December 26, 2005 - 13 - W39F010 Revision A4 ...
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... Embedded Programming Algorithm Increment Address Program Command Sequence (Address/Command): Start Write Program Command Sequence (see below) #Data Polling/ Toggle bit No Last Address ? Yes Programming Completed 5555H/AAH 2AAAH/55H 5555H/A0H Program Address/Program Data - 14 - W39F010 Pause T BP ...
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... Chip Erase Command Sequence (Address/Command): 5555H/AAH 2AAAH/55H 5555H/80H 5555H/AAH 2AAAH/55H 5555H/10H Start (see below) Successfully Completed Erasure Completed Individual Page Erase Command Sequence (Address/Command): 5555H/AAH 2AAAH/55H 5555H/80H 5555H/AAH 2AAAH/55H Page Address/50H Publication Release Date: December 26, 2005 - 15 - W39F010 Pause PEC Revision A4 ...
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... VA = Byte address for programming = Any of the page addresses within Read Byte the page being erased during page erase operation =Any of the device addresses being erased during chip operation DQ7 = Data ? Yes Pass Start Read Byte (DQ0 - DQ7) Address = Don't Care DQ6 = Toggle ? No Pass - 16 - W39F010 ...
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... Load data AA to address 5555 Load data 55 to address 2AAA Load data lock 16K Boot Block to address 5555 Load data XX 1FFFF(XX) to lock Top Boot Block to 00000(XX) to lock Bottom Boot Block address 1FFFF/0 Pause T Publication Release Date: December 26, 2005 - 17 - W39F010 BP Exit Revision A4 ...
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... Read address = 0001 data = A1 (4) Read address=02/1FFF2 for Bottom/Top data: in DQ1="1" or "0" for 16K Boot Block ; device code is read for W39F010 Product Identification Exit(6) Load data AA to address 5555 Load data 55 to address 2AAA Load data F0 ...
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... OUT 2 -0 SYMBOL CONDITIONS OUT OUT Publication Release Date: December 26, 2005 - 19 - W39F010 RATING UNIT -2 +70 qC -65 to +125 qC -2.0 to +7.0 V -2.0 to +13.0 V LIMITS UNIT MIN. TYP. MAX ...
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... AC Test Conditions PARAMETER Input Pulse Levels Input Rise/Fall Time Input/Output Timing Level Output Load 9.2 AC Test Load and Waveform (Including Jig and Scope) Input <5 nS 1.5V/1.5V 1 TTL Gate and C D OUT 30 pF Output 1.5V 1.5V Test Point Test Point - 20 - W39F010 CONDITIONS = +5V 1.8K : 1.3K : ...
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... OEH T 100 CP T 100 WP T 100 WPH 12.5 EP and (b) low level signal's reference level Publication Release Date: December 26, 2005 - 21 - W39F010 W39F010-90 UNIT MIN. MAX MAX. UNIT ...
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... Data Polling Output Delay #OE to Toggle Bit Output Delay #CE to Toggle Bit Output Delay SYMBOL T . READ WRITE PU W39F010-70 SYM. MIN. MAX OEP CEP OET CET - 22 - W39F010 TYPICAL UNIT 100 W39F010-90 UNIT MIN. MAX ...
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... Controlled Command Write Cycle Timing Diagram Address A16-0 #CE #OE #WE DQ7 OLZ T CLZ T OH Data Valid OES Data Valid Publication Release Date: December 26, 2005 - 23 - W39F010 T OHZ T CHZ High-Z Data Valid OEH T WPH T DH Revision A4 ...
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... T #WE SB0 OES Six-byte code for 5V-only software chip erase 5555 5555 2AAA 2AAA WPH SB2 SB3 SB4 SB1 - 24 - W39F010 T CPH CP T OEH T DS Data Valid T DH 5555 Internal Erase starts SB5 ...
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... Six-byte commands for 5V-only Page Erase 5555 5555 2AAA 2AAA WPH SB2 SB3 SB4 SB1 An T CEP T OEH T OEP Publication Release Date: December 26, 2005 - 25 - W39F010 Internal Erase starts SB5 OES X X Revision A4 ...
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... Timing Waveforms, Continued 10.7 Toggle Bit Timing Diagram Address A16-0 #WE #CE #OE DQ6 T OEH W39F010 T OES ...
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... W39F010T-90B 90 W39F010Q-70B 70 W39F010Q-90B 90 W39F010P-70B 70 W39F010P-90B 90 W39F010P-70Z 70 W39F010P-90Z 90 Notes: 1. Winbond reserves the right to make changes to its products without prior notice. 2. Purchasers are responsible for performing appropriate quality assurance testing on products intended for use in applications where personal injury might occur as a consequence of product failure. ...
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... HOW TO READ THE TOP MARKING Example: The top marking of 32-pin PLCC W39F010P-70 W39F010P-70 2138977A-A12 149OBSA st 1 line: winbond logo nd 2 line: the part number: W39F010P- line: the lot number th 4 line: the tracking code: 149 149: Packages made in '01, week 49 O: Assembly house ID: A means ASE, O means OSE, ...etc revision ...
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... Notes Base Plane Seating Plane Publication Release Date: December 26, 2005 - 29 - W39F010 Dimension in inches Dimension in mm Symbol Min. Nom. Max. Nom. Min. Max. A 0.210 5.33 A 0.010 0. 0.150 0.155 0.160 3.81 3.94 4. 0.016 0.018 0.022 ...
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... TSOP ( mm 0.10(0.004 W39F010 Dimension in Inches Dimension in mm Symbol Min. Nom. Max. Min. Nom. Max 1.20 0.047 0.002 0.006 0.05 0. 0.95 0.037 0.039 0.041 1.00 1. 0.007 0.008 0.17 0.20 0.23 0.009 c 0.005 0.006 ...
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... Dimensions D & not include interlead flash. 2. Dimension b1 does not include dambar protrusion/intrusion. 3. Controlling dimension: Inches General appearance spec. should be based on final Publication Release Date: December 26, 2005 - 31 - W39F010 Dimension in Inches Dimension in mm Min. Nom. Max. Min. Nom. Max. A 0.140 3.56 A 0.020 0. ...
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... Correct Embedded #Data Polling Algorithm Change IDD from 10/20 mA to15/30 mA (typ./max.) 16 Change ISB2 from 20/50 2A to15/50 2A (typ./max Rename TSOP ( mm) as STSOP ( mm) 24 Add HOW TO READ THE TOP MARKING 27 Add Important Notice 27 Add 32-pin PLCC lead free part - 32 - W39F010 DESCRIPTION ...
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... Winbond customers using or selling these products for use in such applications their own risk and agree to fully indemnify Winbond for any damages resulting from such improper use or sales. Important Notice Publication Release Date: December 26, 2005 - 33 - W39F010 Revision A4 ...