km29u64000it Samsung Semiconductor, Inc., km29u64000it Datasheet
km29u64000it
Related parts for km29u64000it
km29u64000it Summary of contents
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... KM29U64000T, KM29U64000IT Document Title Bit NAND Flash Memory Revision History Revision No. History 0.0 Initial issue. 1.0 Data Sheet, 1998 1.1 Data Sheet. 1999 1) Added CE don’ t care mode during the data-loading and reading The attached datasheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right to change the specifications ...
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... KM29U64000T, KM29U64000IT Bit NAND Flash Memory FEATURES Voltage Supply : 2.7V ~ 3.6V Organization - Memory Cell Array : (8M + 256K)bit x 8bit - Data Register : (512 + 16)bit x8bit Automatic Program and Erase - Page Program : (512 + 16)Byte - Block Erase : (8K + 256)Byte 528-Byte Page Read Operation - Random Access : 7 s(Max.) - Serial Page Access : 50ns(Min.) Fast Write Cycle Time - Program time : 200 s(typ ...
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... KM29U64000T, KM29U64000IT Figure 1. FUNCTIONAL BLOCK DIAGRAM X-Buffers Latches & Decoders Y-Buffers Latches & Decoders Command Command Register CE Control Logic RE & High Voltage WE Generator CLE ALE WP Figure 2. ARRAY ORGANIZATION 16K Row 1st half Page Register (=1024 Block) ...
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... KM29U64000T, KM29U64000IT PRODUCT INTRODUCTION The KM29U64000 is a 66Mbit(69,206,016 bit) memory organized as 16,384 rows by 528 columns. Spare sixteen columns are located from column address of 512 to 527. A 528-byte data register is connected to memory cell arrays accommodating data trans- fer between the I/O buffers and memory during page read and page program operations. The memory array is made cells that are serially connected to form a NAND structure ...
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... KM29U64000T, KM29U64000IT PIN DESCRIPTION Command Latch Enable(CLE) The CLE input controls the path activation for commands sent to the command register. When active high, commands are latched into the command register through the I/O ports on the rising edge of the WE signal. Address Latch Enable(ALE) The ALE input controls the path activation for address and input data to the internal address/data register ...
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... Output High Voltage Level Output Low Voltage Level Output Low Current(R/B) I Symbol BIAS T STG I OS Q+0.3V which, during transitions, may overshoot KM29U64000IT:T A Min Typ. V 2.7 3 (Recommended operating conditions otherwise noted.) Test Conditions I ...
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... During its lifetime of 10 years and/or 1million program/erase cycles,the minimum number of valid blocks are guaran- teed though its initial number could be reduced. (Refer to the attached technical notes) 2. The 1st block, which is placed on 00h block address, is guaranteed valid block AC TEST CONDITION (KM29U64000T KM29U64000IT:T A Parameter Input Pulse Levels Input Rise and Fall Times Input and Output Timing Levels Output Load (3 ...
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... KM29U64000T, KM29U64000IT AC Timing Characteristics for Command / Address / Data Input Parameter CLE Set-up Time CLE Hold Time CE Setup Time CE Hold Time WE Pulse Width ALE Setup Time ALE Hold Time Data Setup Time Data Hold Time Write Cycle Time WE High Hold Time AC Characteristics for Operation ...
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... KM29U64000T, KM29U64000IT NAND Flash Technical Notes Invalid Block(s) Invalid blocks are defined as blocks that contain one or more invalid bits whose reliability is not guaranteed by Samsung. Typically, an invalid block will contain a single bad bit. The information regarding the invalid block( called as the invalid block informa- tion ...
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... KM29U64000T, KM29U64000IT NAND Flash Technical Notes (Continued) Error in write or read operation Over its life time, the additional invalid blocks may occur. Through the tight process control and intensive testing, Samsung mini- mizes the additional block failure rate, which is projected below 0.1% up until 1million program/erase cycles. Refer to the qualification report for the actual data ...
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... KM29U64000T, KM29U64000IT NAND Flash Technical Notes (Continued) Erase Flow Chart Start Write 60H Write Block Address Write D0H Write 70H SR R Yes * No Erase Error SR Yes Erase Completed : If erase operation results in an error, map out * the failing block and replace it with another block. ...
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... KM29U64000T, KM29U64000IT Pointer Operation of KM29U64000 The KM29U64000 has three read modes to set the destination of the pointer. The pointer is set to "A" area by the "00h" command, to "B" area by the "01" command, and to "C" area by the "50h" command. Table 1 shows the destination of the pointer, and figure 2 shows the block diagram of its operations ...
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... KM29U64000T, KM29U64000IT System Interface Using CE don’ t -care. For a easier system interface, CE may be inactive during the data-loading or sequential data-reading as shown below. The internal 528byte page registers are utilized as seperate buffers for this operation and the system design gets more flexible. In addition, for voice or audio applications which use slow cycle time on the order of u-seconds, de-activating CE during the data-loading and read- ing would provide significant savings in power consumption ...
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... KM29U64000T, KM29U64000IT * Command Latch Cycle CLE ALE I Address Latch Cycle CLE CE WE ALE I CLH CLS ALH ALS Command CLS WH t ALS ...
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... KM29U64000T, KM29U64000IT * Input Data Latch Cycle CLE CE t ALS ALE I/O ~ DIN Sequential Out Cycle after Read R/B NOTES : Transition is measured 200mV from steady state voltage with load DIN 1 ...
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... KM29U64000T, KM29U64000IT * Status Read Cycle CLE I READ1 OPERATION (READ ONE PAGE) CLE ALE 00h or 01h I Column Address R/B t CLS CLS t CLH WHR 70H AR2 ...
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... KM29U64000T, KM29U64000IT READ1 OPERATION (INTERCEPTED BY CE) CLE CE WE ALE I/O ~ 00h or 01h Column Address R/B READ2 OPERATION (READ ONE PAGE) CLE CE WE ALE I/O ~ 50H R/B M Address AR2 tRR Dout N Dout N Page(Row) ...
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... KM29U64000T, KM29U64000IT SEQUENTIAL ROW READ OPERATION CLE CE WE ALE RE 00H I R/B M PAGE PROGRAM OPERATION CLE ALE RE 80H I Sequential Data Column Page(Row) Input Command Address Address R/B Dout Dout Dout N+1 N+2 Busy ...
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... KM29U64000T, KM29U64000IT BLOCK ERASE OPERATION CLE ALE RE 60H I Block Address R/B Auto Block Erase Setup Command MANUFACTURE & DEVICE ID READ OPERATION CLE CE WE ALE RE I/O ~ 90H 0 7 Read ID Command (ERASE ONE BLOCK BERS DOH 22 Busy ...
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... KM29U64000T, KM29U64000IT DEVICE OPERATION PAGE READ Upon initial device power up, the device defaults to Read1 mode. This operation is also initiated by writing 00H to the command reg- ister along with three address cycles. Once the command is latched, it does not need to be written for the following page read oper- ation ...
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... KM29U64000T, KM29U64000IT Figure 4. Read2 Operation CLE CE WE ALE R/B RE 50H Start Add.(3Cycle) I & Don't Care) Figure 5. Sequential Row Read1 Operation R/B I 00H Start Add.(3Cycle) 01H & (SE=L, 00H Command) 1st half array ...
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... KM29U64000T, KM29U64000IT Figure 6. Sequential Row Read2 Operation(SE=fixed low) R/B 50H Start Add.(3Cycle) I & Don t Care) PAGE PROGRAM The device is programmed basically on a page basis, but it does allow multiple partial page programming of a byte or consecutive bytes up to 528 single page program cycle ...
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... KM29U64000T, KM29U64000IT BLOCK ERASE The Erase operation is done on a block(8K Byte) basis. Block address loading is accomplished in two cycles initiated by an Erase Setup command(60H). Only address A 13 block address loading initiates the internal erasing process. This two-step sequence of setup followed by execution command ensures that memory contents are not accidentally erased due to external noise conditions ...
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... KM29U64000T, KM29U64000IT READ ID The device contains a product identification mode, initiated by writing 90H to the command register, followed by an address input of 00H. Two read cycles sequentially output the manufacture code(ECH), and the device code (E6H) respectively. The command regis- ter remains in Read ID mode until further commands are issued to it. Figure 9 shows the operation sequence. ...
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... KM29U64000T, KM29U64000IT READY/BUSY The device has a R/B output that provides a hardware method of indicating the completion of a page program, erase and random read completion. The R/B pin is normally high but transitions to low after program or erase command is written to the command reg- ister or random read is started after address loading. It returns to high when the internal controller has finished the operation. The pin is an open-drain driver thereby allowing two or more R/B outputs to be Or-tied ...
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... KM29U64000T, KM29U64000IT PACKAGE DIMENSIONS 44(40) LEAD PLASTIC THIN SMALL OUT-LINE PACKAGE TYPE(II) 44(40) - TSOP2 - 400F #44(40) #1 18.81 Max. 0.741 18.41 0.10 0.725 0.004 0.805 0.35 0.10 0.032 0.014 0.004 FLASH MEMORY 0.25 0.010 TYP #23(21) #22(20) 0.15 0.006 0.80 0.0315 26 Unit :mm/Inch 0~8 0.50 0.020 +0.10 -0.05 +0.004 -0.002 0.10 MAX 0.004 ...