gvt73128s24 ETC-unknow, gvt73128s24 Datasheet
gvt73128s24
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gvt73128s24 Summary of contents
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... SRAM +3.3V SUPPLY, THREE MEGABIT THREE CHIP ENABLES GENERAL DESCRIPTION The GVT73128A24 and GVT73128S24 are organized as a 131,072 x 24 SRAM using a four-transistor memory cell with a high performance, silicon gate, low-power CMOS process. Galvantech SRAMs are fabricated using triple-layer polysilicon, double-layer metal technology. ...
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... GALVANTECH FUNCTIONAL BLOCK DIAGRAM VCC VSS A0 A16 Note: BE0#, BE1# and BE2# are available for GVT73128S24 only. August 31, 1999 Rev. 8/99 GVT73128A24/GVT73128S24 , 128K X 24 ASYNCHRONOUS SRAM MEMORY ARRAY 128K X 24 COLUMN DECODER 2 Galvantech, Inc. reserves the right to change products or specifications without notice. ...
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... T NC A10 A8 WE OE# Note: BE0#, BE1# and BE2# are available for GVT73128S24 in 100-pin TQFP package only. For GVT73128A24 in 100-pin TQFP package, pin# 47, 48 and 49 are NC. August 31, 1999 Rev. 8/99 , 128K X 24 ASYNCHRONOUS SRAM 128Kx24, 100-PIN TQFP (Top View A16 ...
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... VSS Groun 7A, 7B, 7T GVT73128A24/GVT73128S24 DESCRIPTION Address Inputs: These inputs determine which cell is addressed. Write Enable: This input determines if the cycle is a READ or WRITE cycle. WE# is LOW for a WRITE cycle and HIGH for a READ cycle. Chip Enable: These inputs are used to enable the device ...
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... BYTE 1 WRITE (DQ8-DQ15) BYTE 2 WRITE (DQ16-DQ23 OUTPUT DISABLE Note: BE0#, BE1# and BE2# are available for GVT73128S24 in 100-pin TQFP package only. August 31, 1999 Rev. 8/99 , 128K X 24 ASYNCHRONOUS SRAM WE# OE# BE0# BE1# BE2 ...
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... IL O < VCC VCC SYM TYP ; VCC =MAX 165 MAX SB1 I 5 SB2 CONDITIONS SYMBOL MHz C I VCC = 3.3V C I/O 6 GVT73128A24/GVT73128S24 MIN MAX UNITS 2.2 VCC+0.5 V 2.2 4.6 V -0.5 0 2.4 V 0.4 V 3.0 3 -10 -12 -15 UNIT S NOTES 150 130 ...
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... WP2 WP1 5 LZWE 3 3 HZW GVT73128A24/GVT73128S24 - MAX MIN MAX UNIT S NOTES ...
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... RC = Read Cycle Time. 12. Chip Enable and Write Enable can initiate and terminate a WRITE cycle. 13. Capacitance derating applies to capacitance different from the load capacitance shown in Fig. 1. 14. Typical values are measured at 3.3V HZCE is less 8 GVT73128A24/GVT73128S24 1.5V Fig. 1 OUTPUT LOAD EQUIVALENT 3.3v 317 ...
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... GALVANTECH ADDR Q PREVIOUS DATA VALID CE# CE1# CE2 BE0# BE1# BE2# OE# Q Note: BE0#, BE1# and BE2# are available for GVT73128S24 only. August 31, 1999 Rev. 8/99 GVT73128A24/GVT73128S24 , 128K X 24 ASYNCHRONOUS SRAM ( READ CYCLE NO VALID ( READ CYCLE NO. 2 ...
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... D Q (Write Enable Controlled with Output Enable OE# inactive HIGH) ADDR CE# CE1# CE2 BE0# BE1# BE2# WE Note: BE0#, BE1# and BE2# are available for GVT73128S24 only. August 31, 1999 Rev. 8/99 GVT73128A24/GVT73128S24 , 128K X 24 ASYNCHRONOUS SRAM (7, 12, 13) WRITE CYCLE NO ...
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... CE2 BE0# BE1# BE2# WE ADDR BE0# BE1# BE2# CE2 CE# CE1# WE Note: BE0#, BE1# and BE2# are available for GVT73128S24 only. August 31, 1999 Rev. 8/99 GVT73128A24/GVT73128S24 , 128K X 24 ASYNCHRONOUS SRAM (12, 13) WRITE CYCLE NO. 3 (Chip Enable Controlled ...
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... GALVANTECH 100 Pin TQFP Package Dimensions # 1 1.40 + 0.05 1.60 Max Note: All dimensions in Millimeters August 31, 1999 Rev. 8/99 GVT73128A24/GVT73128S24 , 128K X 24 ASYNCHRONOUS SRAM 16.00 + 0.10 14.00 + 0.10 0.65 Basic 0.30 + 0.08 12 Galvantech, Inc. reserves the right to change products or specifications without notice. 0.60 + 0.15 ...
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... TYP. 0.56 REF. Note: All dimensions in Millimeters August 31, 1999 Rev. 8/99 , 128K X 24 ASYNCHRONOUS SRAM 22.00 + 0.20 20.32 1. BOTTOM VIEW 19.50 + 0.10 TOP VIEW SIDE VIEW 13 GVT73128A24/GVT73128S24 0.60 + 0.10 Galvantech, Inc. reserves the right to change products or specifications without notice. ...
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... Part Number (No Byte Enable Controls) GVT 73128S24 Galvantech Prefix Part Number (With Byte Enable Controls) August 31, 1999 Rev. 8/99 GVT73128A24/GVT73128S24 , 128K X 24 ASYNCHRONOUS SRAM 14 Galvantech, Inc. reserves the right to change products or specifications without notice. Temperature (Blank = Commercial I = Industrial) Speed ( 9 = 9ns 10ns, ...