gvt72024a8 ETC-unknow, gvt72024a8 Datasheet

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gvt72024a8

Manufacturer Part Number
gvt72024a8
Description
Traditional Pinout 128k Sram
Manufacturer
ETC-unknow
Datasheet

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TI
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Part Number:
gvt72024a8J-12
Manufacturer:
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FEATURES
• Fast access times: 10, 12, 15and 20ns
• Fast OE# access times: 5, 6, 7 and 8ns
• Single +5V +10% power supply
• Fully static -- no clock or timing strobes necessary
• All inputs and outputs are TTL-compatible
• Three state outputs
• Easy memory expansion with CE1#, CE2 and OE# options
• High-performance, low-power consumption, CMOS
OPTIONS
• Timing
• Packages
• Power consumption
• Temperature
Galvantech, Inc. 3080 Oakmead Village Drive, Santa Clara, CA 95051
Tel (408) 566-0688
Rev. 2/98
GALVANTECH
ASYNCHRONOUS
SRAM
double-poly, double-metal process
10ns access
12ns access
15ns access
20ns access
32-pin SOJ (400 mil)
32-pin SOJ (300 mil)
32-pin TSOP (type I)
Standard
Low
Commercial
Industrial
Fax (408) 566-0699
MARKING
-10
-12
-15
-20
J
SJ
TS
None
L
None
I
(
(
0°C
-40°C
, INC.
to
70°C)
to
85°C)
TRADITIONAL PINOUT 128K X 8 SRAM
GENERAL DESCRIPTION
using a four-transistor memory cell with a high performance,
silicon gate, low-power CMOS process. Galvantech SRAMs
are fabricated using double-layer polysilicon, double-layer
metal technology.
timing strobes. For increased system flexibility and
eliminating bus contention problems, this device offers two
chip enables (CE1# and CE2) along with output enable (OE#)
for this organization.
HIGH. With chip being enabled, writing to this device is
accomplished when write enable (WE#) is LOW and reading
is accomplished when (OE#) go LOW with (WE#) remaining
HIGH. The device offers a low power standby mode when
chip is not selected. This allows system designers to meet low
standby power requirements.
The GVT72024A8 is organized as a 131,072 x 8 SRAM
Static design eliminates the need for external clocks or
The chip is enabled when CE1# is LOW and CE2 is
128K x 8 SRAM
WITH TWO CHIP ENABLE
TRADITIONAL PINOUT
WE#
VCC
CE2
A11
A13
A15
A16
A14
A12
NC
A9
A8
A7
A6
A5
A4
10
11
12
13
14
15
16
1
2
3
4
5
6
7
8
9
DQ1
DQ2
DQ3
VSS
A16
A14
A12
NC
A7
A6
A5
A4
A3
A2
A1
A0
32-Pin TSOP (Type I)
PIN ASSIGNMENT
PIN ASSIGNMENT
10
11
12
13
14
15
16
1
2
3
4
5
6
7
8
9
32-Pin SOJ
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
GVT72024A8
VCC
A15
CE2
WE#
A13
A8
A9
A11
OE#
A10
CE1#
DQ8
DQ7
DQ6
DQ5
DQ4
Galvantech, Inc. reserves the right to change
products or specifications without notice.
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
OE#
A10
CE1#
DQ8
DQ7
DQ6
DQ5
DQ4
VSS
DQ3
DQ2
DQ1
A0
A1
A2
A3

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gvt72024a8 Summary of contents

Page 1

... TRADITIONAL PINOUT 128K X 8 SRAM 128K x 8 SRAM WITH TWO CHIP ENABLE TRADITIONAL PINOUT GENERAL DESCRIPTION The GVT72024A8 is organized as a 131,072 x 8 SRAM using a four-transistor memory cell with a high performance, silicon gate, low-power CMOS process. Galvantech SRAMs are fabricated using double-layer polysilicon, double-layer metal technology. ...

Page 2

... Output Enable: This active LOW input enables the output drivers. Input/ SRAM Data I/O: Data inputs and data outputs Output VCC Supply Power Supply 10% VSS Supply Ground 2 GVT72024A8 POWER DOWN POWER ACTIVE ACTIVE ACTIVE STANDBY STANDBY DESCRIPTION Galvantech, Inc. reserves the right to change products or specifications without notice. ...

Page 3

... VCC SYM TYP & CE2 > Icc 80 standard IL IH standard ; VCC = MAX SB1 standard I 0.02 SB2 CONDITIONS SYMBOL MHz C I VCC = 5V C I/O 3 GVT72024A8 MIN MAX UNITS 2.2 VCC+1 V -0.5 0 2.4 V 0.4 V 4.5 5.5 V -10 -12 -15 -20 POWER 210 180 150 110 ...

Page 4

... WP2 WP1 LZWE 3 4 HZWE GVT72024A8 - MAX MIN MAN UNITS NOTES ...

Page 5

... Fig. 1. 14. Typical values are measured at 5V HZCE is less CONDITIONS SYMBOL Vcc = 2V CCDR I Vcc = 3V CCDR t CDR GVT72024A8 1.5V Fig. 1 OUTPUT LOAD EQUIVALENT +5V 480 Q 255 and 20ns cycle time. MIN TYP MAX UNITS 2 ...

Page 6

... READ CYCLE NO VALID (7, 8, 10, 12) READ CYCLE NO AOE t LZOE t ACE t LZCE HIGH Z 6 GVT72024A8 DATA RETENTION MODE t RC DATA VALID t HZCE t HZOE DATA VALID DON'T CARE UNDEFINED Galvantech, Inc. reserves the right to change products or specifications without notice. ...

Page 7

... WP2 DATA VALID t HZWE (12, 13) WRITE CYCLE NO WP1 DATA VALID HIGH Z 7 GVT72024A8 LZWE HIGH DON'T CARE UNDEFINED Galvantech, Inc. reserves the right to change products or specifications without notice. ...

Page 8

... February 5, 1998 Rev. 2/98 , INC. TRADITIONAL PINOUT 128K X 8 SRAM (12, 13) WRITE CYCLE NO. 3 (Chip Enable Controlled WP1 DATA VALID HIGH Z 8 GVT72024A8 DON'T CARE Galvantech, Inc. reserves the right to change products or specifications without notice. ...

Page 9

... MIN .825 (20.96) .810 (20.57) .340 (8.64) .330 (8.38) .050 (1.27) TYP .020 (0.51) .015 (0.38) MAX or typical, min where noted. MIN 9 GVT72024A8 .380 (9.65) .360 (9.14) .030 (0.76) MIN .140 (3.55) .120 (3.04) .095 (2.41) .080 (2.03) .274 (6.95) .254 (6.44) .025 (0.63) Galvantech, Inc. reserves the right to change products or specifications without notice. ...

Page 10

... February 5, 1998 Rev. 2/98 , INC. TRADITIONAL PINOUT 128K X 8 SRAM .795 (20.20) .780 (19.80) .728 (18.50) .720 (18.30) MAX or typical, max where noted. MIN 10 GVT72024A8 .319 (8.10) .311 (7.90) .041 (1.05) .037 (0.95) Temperature (Blank = Commercial I = Industrial) Power (Blank= Standard, L= Low Power) Speed (10 = 10ns, 12= 12ns 15ns 20ns) Package (J = 400 mil SOJ, ...

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