w49v002fa Winbond Electronics Corp America, w49v002fa Datasheet
w49v002fa
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w49v002fa Summary of contents
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... The W49V002FA is a 2-megabit, 3.3-volt only CMOS flash memory organized as 256K device can be programmed and erased in-system with a standard 3.3V power supply. A 12-volt V not required. The unique cell architecture of the W49V002FA results in fast program/erase operations with extremely low current consumption. This device can operate at two modes, Programmer bus interface mode and FWH bus interface mode ...
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... A0(ID0) 20 A[10:0] * A1(ID1) 19 A2(ID2) 18 A3(ID3) 17 DQ[7:0] * # GND * RSV * W49V002FA 3FFFF BOOT BLOCK 16K BYTES 3C000 3BFFF PARAMETER Interface BLOCK1 8K BYTES 3A000 39FFF PARAMETER BLOCK2 8K BYTES 38000 37FFF MAIN MEMORY BLOCK1 32K BYTES 30000 2FFFF MAIN MEMORY BLOCK2 64K BYTES Program- ...
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... Interface Specification. Through the FWH[3:0] to communicate with the system chipset . Read (Write) Mode In Programmer interface mode, the read (write) operation of the W49V002FA is controlled by #OE (#WE). The #OE(#WE) is held low for the host to obtain(write) data from(to) the outputs(inputs). #OE is the output control and is used to gate data from the output pins. The data bus is in high impedance state when #OE is high. As for in the FWH interface mode, the read or write is determined by the " ...
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... Hardware Data Protection The integrity of the data stored in the W49V002FA is also hardware protected in the following ways: (1) Noise/Glitch Protection: A #WE pulse of less than duration will not initiate a write cycle. ...
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... Write Status Detection 6 In addition to data polling, the W49V002FA provides another method for determining the end of a program cycle. During the internal program or erase cycle, any consecutive attempts to read DQ produce alternating 0's and 1's. When the program or erase cycle is completed, this toggling between 0's and 1's will stop ...
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... AA 2AAA 55 5555 80 5555 AA 2AAA 55 5555 A0 5555 AA 2AAA 55 5555 80 5555 AA 2AAA 55 5555 90 5555 AA 2AAA 55 5555 F0 XXXX W49V002FA 4TH CYCLE 5TH CYCLE 6TH CYCLE Addr. Data Addr. Data Addr. Data 5555 AA 2AAA 55 5555 10 5555 AA 2AAA 5555 AA 2AAA 55 ...
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... Short Wait, "0110b" means Long Wait, "1001b" for DMA only, "1010b" means error, and other values are reserved. DATA 2 Data Phase for Memory Cycle. The data transfer least significant nibble first and most significant nibble last. (i.e. DQ[3:0] on FWH[3:0] first , then DQ[7:4] on FWH[3:0] last.) W49V002FA DESCRIPTION Publication Release Date: February 19, 2002 - 7 - Revision A2 ...
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... Embedded Programming Algorithm Increment Address Program Command Sequence (Address/Command): Start Write Program Command Sequence (see below) #Data Polling/ Toggle bit No Last Address ? Yes Programming Completed 5555H/AAH 2AAAH/55H 5555H/A0H Program Address/Program Data - 8 - W49V002FA Pause T BP ...
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... Start Write Erase Command Sequence (see below) #Data Polling or Toggle Bit Successfully Completed Erasure Completed Individual Sector Erase Command Sequence (Address/Command): 5555H/AAH 2AAAH/55H 5555H/80H 5555H/AAH 2AAAH/55H Sector Address/30H Publication Release Date: February 19, 2002 - 9 - W49V002FA Pause SEC Revision A2 ...
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... Address = VA No DQ7 = Data ? Yes Pass Start Read Byte (DQ0 - DQ7) Address = Don't Care Yes DQ6 = Toggle ? No Pass - 10 - W49V002FA = Any of the sector addresses within the sector being erased during sector erase operation = Valid address equals any sector group address during chip erase ...
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... Read address = 00001 data = 32 (Hex) (4) Read address = 00002 DQ0 of data outputs = 1/0 A0 (Hex) ; device code is read for Publication Release Date: February 19, 2002 - 11 - W49V002FA Product Identification Exit(6) Load data AA to address 5555 Load data 55 to address 2AAA Load data F0 to address 5555 ...
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... Boot Block Lockout Enable Acquisition Flow Boot Block Lockout Feature Set Flow Load data AA to address 5555 Load data 55 to address 2AAA Load data 80 to address 5555 Load data AA to address 5555 Load data 55 to address 2AAA Load data 40 to address 5555 Pause T BP Exit - 12 - W49V002FA ...
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... In Read or Write mode, all DQs open Address inputs = 3.0V/0V MHz V = GND GND to V OUT 2 -0.1mA OH Publication Release Date: February 19, 2002 - 13 - W49V002FA RATING UNIT -0 +70 C -65 to +150 LIMITS UNIT MIN. TYP. MAX. ...
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... DD DD, internal operation , CLK = 33 MHz, DD all inputs = 0 0 DD, no internal operation - - - - SYMBOL T . READ WRITE PU SYMBOL CONDITIONS I/O I W49V002FA LIMITS UNIT MIN. TYP. MAX 100 - -0 -0. 1.35V - ...
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... Input Rise/Fall Time Input/Output Timing Level Output Load AC Test Load and Waveform D OUT 30 pF (Including Jig and Scope) CONDITIONS < 1.5V/1.5V 1 TTL Gate and +3.3V 1.8K Input 0.9V DD 1.3K 1.5V 0V Test Point Publication Release Date: February 19, 2002 - 15 - W49V002FA Output 1.5V Test Point Revision A2 ...
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... CWH T 100 - WP T 100 - WPH OEH 0.15 EC SYMBOL W49V002FA MIN OEP T - OET - 16 - W49V002FA UNIT MAX 200 nS 100 MAX. UNIT - 100 S 0.2 S UNIT MAX ...
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... Column Address Row Address OLZ Row Address CWH Data Valid Publication Release Date: February 19, 2002 - 17 - W49V002FA Column Address Row Address OHZ High-Z Data Valid T OEH T WPH Revision A2 ...
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... Row Address A[6:0] are mapped to the internal A[17:11]. #DATA Polling Timing Diagram A[10:0] (Internal A[17:0 #WE #OE DQ7 Byte Program Cycle 5555 2AAA 5555 Programmed Address WPH T WP Byte 1 Byte 0 Byte OEP W49V002FA Data- Internal Write Start Byte ...
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... Column Address A[10:0] are mapped to the internal A[10:0], Row Address A[6:0] are mapped to the internal A[17:11]. T OET Six-byte code for 3.3V-only software chip erase 2AAA 5555 5555 2AAA WPH SB2 SB3 SB4 SB1 Publication Release Date: February 19, 2002 - 19 - W49V002FA 5555 SB5 Revision A2 ...
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... SB3 SB1 SB4 Row Address A[6:0] are mapped to the internal A[17:11]. Six-byte code for 3.3V-only software sector erase 2AAA 5555 5555 2AAA WPH SB2 SB3 SB4 SB1 - 20 - W49V002FA 5555 Internal Erasure Starts SB5 Internal Erase starts SB5 ...
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... W49V002FA MIN CYC SYM. MIN PRST T 100 KRST T 100 RSTP T - RSTF T 1 RST Publication Release Date: February 19, 2002 - 21 - W49V002FA Input Output 0.4V 0. Test Point Test Point UNIT MAX TYP. MAX. UNIT - - ...
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... Address M Size 0000b] A[15:12] A[11:8] A[7:4] A[3:0] Load Address in 7 Clocks T CYC Address M Size XXXXb A[7:4] XXA[17:16]b A[15:12] A[11:8] A[3:0] 0000b Load Address in 7 Clocks - 22 - W49V002FA T KQ TAR Sync Data Tri-State 0000b D[3:0] D[7:4] TAR 1111b 2 Clocks Data out 2 Clocks 1 Clock TAR Sync Data D[7:4] 1111b 0000b TAR D[3:0] ...
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... Address M Size 0000b A[11:8] A[7:4] A[3:0] XXA[17:16]b A[15:12] Load Ain in 7 Clocks Write the 4th command(target location to be programmed) to the device in FWH mode. Publication Release Date: February 19, 2002 - 23 - W49V002FA Data TAR Sync TAR 1111b 0000b Tri-State 1111b 1010b 1010b Load Data "AA" Clocks ...
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... Read the DQ7 to see if the internal write complete or not. Address M Size XXXXb 0000b An[15:12] An[11:8] An[7:4] An[3:0] XXA[17:16]b Load Address in 7 Clocks When internal write complete, the DQ7 will equal to Dn7 W49V002FA Data TAR Sync TAR Dn[3:0] Dn[7:4] 1111b Tri-State 0000b 1111b Tri-State Load Data "Dn" ...
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... Address M Size XXXXb XXXXb XXXXb XXXXb XXXXb 0000b XXXXb Load Address in 7 Clocks When internal write complete, the DQ6 will stop toggle. Publication Release Date: February 19, 2002 - 25 - W49V002FA Data TAR Sync TAR D[3:0] D[7:4] 1111b 0000b 1111b Tri-State Tri-State Load Data "Dn" ...
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... XXXXb XXXXb X101b 0101b 0101b 0101b Load Data "40" Load Address "5555" 7 Clocks in 2 Clocks Write the 6th command to the device in FWH mode W49V002FA Start next Data TAR Sync TAR command 1111b Tri-State 0000b 1111b Tri-State 1010b 1010b Load Data " ...
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... Load Data "10" Load Address "5555" Clocks in 2 Clocks Write the 6th command to the device in FWH mode. Publication Release Date: February 19, 2002 - 27 - W49V002FA Start next TAR Sync TAR command 1111b Tri-State 0000b 1111b Tri-State ...
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... Address M Size XXXXb XXXXb 0000b 0000b SA[15:12] XXXXb XXXXb XXXXb XXA[17:16]b Load Sector Address in 7 Clocks Write the 6th command(target sector to be erased) to the device in FWH mode W49V002FA Start next Data TAR TAR Sync command 1111b Tri-State 0000b 1010b 1010b Tri-State 1111b Load Data " ...
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... FWH[3:0] FWH4 M Size Address 0001b 0000b A[23:20] A[19:16] 0000b 0000b 0000b /0000b /0001b T PRST T KRST T RST F Publication Release Date: February 19, 2002 - 29 - W49V002FA TAR TAR Sync Data Tri-State 1111b D[3:0] D[7:4] 0000b Tri-State 1111b 2 Clocks 1 Clock Data out 2 Clocks 2 Clocks T RSTP T RST Revision A2 Next Start ...
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... Winbond reserves the right to make changes to its products without prior notice. 2. Purchasers are responsible for performing appropriate quality assurance testing on products intended for use in applications where personal injury might occur as a consequence of product failure. HOW TO READ THE TOP MARKING Example: The top marking of 32L-PLCC W49V002FA W49V002FAP 2123055C-082 132GHSA ...
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... Symbol Notes Publication Release Date: February 19, 2002 - 31 - W49V002FA Dimension in Inches Dimension in mm Min. Nom. Max. Min. Nom. Max. A 0.140 3.56 A 0.020 0. 0.105 0.110 0.115 2.67 2.80 2. 0.026 0.032 0.66 0.81 0.028 0.71 ...
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... Winbond Electronics Corporation America 2727 North First Street, San Jose, CA 95134, U.S.A. TEL: 1-408-9436666 FAX: 1-408-5441798 Winbond Electronics Corporation Japan 7F Daini-ueno BLDG, 3-7-18 Shinyokohama Kohoku-ku, Yokohama, 222-0033 TEL: 81-45-4781881 FAX: 81-45-4781800 - 32 - W49V002FA DESCRIPTION ) parameter IHI 0 (min DD; IH DD. for the #INIT pin input spec. ...