w39l010 Winbond Electronics Corp America, w39l010 Datasheet
w39l010
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w39l010 Summary of contents
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... DQ6: Toggle Bit................................................................................................................9 7. TABLE OF OPERATING MODES ............................................................................................ 10 7.1 Device Bus Operations ................................................................................................. 10 7.2 Auto-select Codes (High Voltage Method) ................................................................... 10 7.3 Command Definitions ................................................................................................... 11 7.4 Embedded Programming Algorithm ............................................................................. 12 7.5 Embedded Erase Algorithm.......................................................................................... 13 7.6 Embedded #Data Polling Algorithm.............................................................................. 14 7.7 Embedded Toggle Bit Algorithm ................................................................................... 14 128K u 8 CMOS FLASH MEMORY Publication Release Date: January 9, 2004 - 1 - W39L010 Revision A4 ...
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... Controlled Command Write Cycle Timing Diagram.............................................. 22 9.4 Chip Erase Timing Diagram ......................................................................................... 22 9.5 Page Erase Timing Diagram ........................................................................................ 23 9.6 #DATA Polling Timing Diagram .................................................................................... 23 9.7 Toggle Bit Timing Diagram ........................................................................................... 24 10. ORDERING INFORMATION .................................................................................................... 25 11. HOW TO READ THE TOP MARKING...................................................................................... 25 12. PACKAGE DIMENSIONS ......................................................................................................... 26 12.1 32-pin PLCC ................................................................................................................. 26 12.2 32-pin STSOP ( mm) .......................................................................................... 26 13. VERSION HISTORY ................................................................................................................. W39L010 ...
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... GENERAL DESCRIPTION The W39L010 is a 1Mbit, 3.3-volt only CMOS flash memory organized as 128K u 8 bits. For flexible erase capability, the 1Mbits of data are divided into 32 small even pages with 4 Kbytes. The byte-wide (u 8) data appears on DQ7 DQ0. The device can be programmed and erased in-system with a standard 3 ...
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... DQ0 DQ7 DQ2 23 DQ1 22 #CE DQ0 # # W39L010 DQ0 . OUTPUT . CONTROL BUFFER DQ7 CORE DECODER ARRAY PIN NAME Address Inputs Data Inputs/Outputs Chip Enable Output Enable Write Enable Power Supply Ground No Connections ...
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... Read Mode The read operation of the W39L010 is controlled by #CE and #OE, both of which have to be low for the host to obtain data from the outputs. #CE is used for device selection. When #CE is high, the chip is de-selected and only standby power will be consumed. #OE is the output control and is used to gate data from the output pins ...
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... The manufacturer and device codes may also be read via the command register, for instance, when the W39L010 is erased or programmed in a system without access to high voltage on the A9 pin. The command sequence is illustrated in "Auto-select Codes". Byte 0 ( represents the manufacturercs code (Winbond = DAH) and byte 1 ( device identifier code (W39L010 = 31H) ...
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... The operation is initiated by writing the auto-select command sequence into the command register. Following the command write, a read cycle from address XX00H retrieves the manufacture code of DAH. A read cycle from address XX01H returns the device code (W39L010 = 31H). To terminate the operation necessary to write the auto-select exit command sequence into the register ...
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... DQ7, Data Polling, is "1" at which time the device returns to the read mode. Data Polling must be performed at an address within any of the pages being erased. Refer to the Erase Command flow Chart using typical command strings and bus operations W39L010 ...
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... Erase Algorithm, or page erase time-out (see "Command Definitions"). 6.4.2 DQ6: Toggle Bit The W39L010 also features the "Toggle Bit" method to indicate to the host system that the embedded algorithms are in progress or completed. During an Embedded Program or Erase Algorithm cycle, successive attempts to read (#OE toggling) data from the device at any address will result in DQ6 toggling between one and zero ...
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... TABLE OF OPERATING MODES 7.1 Device Bus Operations ( r0.5V) ID MODE Read Write Standby Write Inhibit Output Disable Auto select Manufacturers ID Auto select Device ID 7.2 Auto-select Codes (High Voltage Method r0.5V) ID DESCRIPTION Manufacturer ID: Winbond Device ID: W39L010 #CE #OE # ...
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... PA = 05XXXh for Page 04XXXh for Page 03XXXh for Page 02XXXh for Page 01XXXh for Page 00XXXh for Page 0 Publication Release Date: January 9, 2004 - 11 - W39L010 5TH CYCLE 6TH CYCLE 7TH CYCLE Addr. Data Addr. Data Addr. Data 2AAA 55 ...
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... Embedded Programming Algorithm Increment Address Program Command Sequence (Address/Command): Start Write Program Command Sequence (see below) #Data Polling/ Toggle bit No Last Address ? Yes Programming Completed 5555H/AAH 2AAAH/55H 5555H/A0H Program Address/Program Data - 12 - W39L010 Pause T BP ...
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... Start (see below) #Data Polling or Toggle Bit Successfully Completed Erasure Completed Individual Page Erase Command Sequence (Address/Command): 5555H/AAH 2AAAH/55H 5555H/80H 5555H/AAH 2AAAH/55H Page Address/50H - 13 - W39L010 Pause PEC Publication Release Date: January 9, 2004 Revision A4 ...
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... Address = VA No DQ7 = Data ? Yes Pass Start Read Byte (DQ0 - DQ7) Address = Don't Care Yes DQ6 = Toggle ? No Pass - 14 - W39L010 = Any of the page addresses within the page being erased during page erase operation =Any of the device addresses being erased during chip operation ...
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... Load data 55 to address 2AAA Load data 70 to address 5555 Load data XX to address 1FFFF lcok 8K Boot Block 1FFFF(XX) to lock Top Boot Block 00000(XX) to lock Bottom Boot Block - 15 - W39L010 Pause 2mS Exit Publication Release Date: January 9, 2004 Revision A4 ...
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... Read address = 0001 data = 31 (4) Read address=02/1FFF2 for Bottom/Top data:in DQ1="1" or "0" for 8K Boot Block ; device code is read for W39L010 Product Identification Exit(6) Load data AA to address 5555 Load data 55 to address 2AAA Load data F0 ...
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... DQs open DD Other inputs = V -0.3V OUT 2 -0 SYMBOL CONDITIONS OUT OUT - 17 - W39L010 RATING UNIT -2 +70 -65 to +125 -2.0 to +4.6 -2.0 to +13.0 LIMITS MIN. TYP. MAX -0.3 - 0 0.45 2 TYP ...
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... AC Test Conditions PARAMETER Input Pulse Levels Input Rise/Fall Time Input/Output Timing Level Output Load 8.5 AC Test Load and Waveform <5 nS 1.5V/1.5V 1 TTL Gate and C +3.3V D OUT 30 pF (Including Jig and Scope) Input Output 3V 1.5V 1.5V 0V Test Point Test Point - 18 - W39L010 CONDITIONS = 1.2K : 2.1K : ...
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... T 0 OEH T 100 CP T 100 WP T 100 WPH and (b) low level signal's reference level Publication Release Date: January 9, 2004 - 19 - W39L010 W39L010-90 UNIT MIN. MAX TYP. ...
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... Toggle Bit Output Delay #CE to Toggle Bit Output Delay SYMBOL T . READ WRITE PU -70 W39L010 SYM. MIN. MAX OEP CEP OET CET - 20 - W39L010 TYPICAL UNIT 100 -90 W39L010 UNIT MIN. MAX ...
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... Controlled Command Write Cycle Timing Diagram Address A16-0 #CE #OE #WE DQ7 OLZ T CLZ T OH Data Valid OES Data Valid Publication Release Date: January 9, 2004 - 21 - W39L010 T OHZ T CHZ High-Z Data Valid OEH T WPH T DH Revision A4 ...
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... T #WE SB0 OES High Z Six-byte code for 3.3V-only software chip erase 5555 5555 2AAA 2AAA WPH SB2 SB3 SB1 SB4 - 22 - W39L010 T CPH T OEH T DS Data Valid T DH 5555 Internal Erase starts SB5 ...
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... Six-byte commands for 3.3V-only Page Erase 5555 5555 2AAA 2AAA WPH SB3 SB2 SB4 SB1 CEP T OEH T OEP W39L010 Internal Erase starts SB5 OES X X Publication Release Date: January 9, 2004 Revision A4 ...
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... Timing Waveforms, continued 9.7 Toggle Bit Timing Diagram Address A16-0 #WE #CE #OE DQ6 T OEH W39L010 T OES ...
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... Winbond reserves the right to make changes to its products without prior notice. 2. Purchasers are responsible for performing appropriate quality assurance testing on products intended for use in applications where personal injury might occur as a consequence of product failure. 11. HOW TO READ THE TOP MARKING Example: The top marking of 32-pin PLCC W39L010P-70 W39L010P-70 2138977A-A12 149OBSA ...
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... STSOP ( mm ð W39L010 Dimension in Inches Dimension in mm Symbol Min. Nom. Max. Min. Nom. Max. A 0.140 3.56 A 0.020 0. 0.105 0.110 0.115 2.67 2.80 2. 0.026 0.032 0.66 0.81 0.028 0.71 ...
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... TEL: 1-408-9436666 FAX: 1-408-5441798 Winbond Electronics Corporation Japan 7F Daini-ueno BLDG, 3-7-18 Shinyokohama Kohoku-ku, Yokohama, 222-0033 TEL: 81-45-4781881 FAX: 81-45-4781800 - 27 - W39L010 DESCRIPTION Write and read Inhibit inhibit write description Winbond Electronics (Shanghai) Ltd. 27F, 2299 Yan An W. Rd. Shanghai, 200336 China TEL: 86-21-62365999 FAX: 86-21-62365998 Winbond Electronics (H ...