k6x4016c3f Samsung Semiconductor, Inc., k6x4016c3f Datasheet
k6x4016c3f
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k6x4016c3f Summary of contents
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... K6X4016C3F Family Document Title 256Kx16 bit Low Power full CMOS Static RAM Revision History Revision No. History 0.0 Initial draft 0.1 Revised Added Commercial Product. Deleted 44-TSOP2-400R Package Type. 1.0 Finalized - Changed I from 10mA to 5mA CC - Changed I 1 from 10mA to 7mA CC - Changed I 2 from 50mA to 30mA ...
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... SAMSUNG ELECTRONICS CO., LTD. reserves the right to change products and specifications without notice. GENERAL DESCRIPTION The K6X4016C3F families are fabricated by SAMSUNG s advanced full CMOS process technology. The families sup- port various operating temperature range and small pack- age types for user flexibility of system design. The families also support low data retention voltage for battery back-up operation with low data retention current ...
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... K6X4016C3F Family PRODUCT LIST Commercial Products(0~70 C) Part Name Function K6X4016C3F-TB55 44-TSOP2-F, 55ns, LL K6X4016C3F-TB70 44-TSOP2-F, 70ns, LL FUNCTIONAL DESCRIPTION ...
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... K6X4016C3F Family RECOMMENDED DC OPERATING CONDITIONS Item Supply voltage Ground Input high voltage Input low voltage Note: 1. Commercial Product otherwise specified A Industrial Product otherwise specified A Automotive Product T =-40 to 125 C, otherwise specified A 2. Overshoot: V +3.0V in case of pulse width CC 3. Undershoot: -3.0V in case of pulse width 30ns 4 ...
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... K6X4016C3F Family AC OPERATING CONDITIONS TEST CONDITIONS (Test Load and Test Input/Output Reference) Input pulse level: 0.8 to 2.4V Input rising and falling time: 5ns Input and output reference voltage: 1.5V Output load (See right): C =100pF+1TTL L C =50pF+1TTL L AC CHARACTERISTICS ( Vcc=4.5~5.5V, Commercial Product Industrial Product: T ...
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... K6X4016C3F Family TIMING DIAGRAMS TIMING WAVEFORM OF READ CYCLE(1) Address Data Out Previous Data Valid TIMING WAVEFORM OF READ CYCLE(2) Address CS UB Data out High-Z NOTES (READ CYCLE and are defined as the time at which the outputs achieve the open circuit conditions and are not referenced to output voltage ...
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... K6X4016C3F Family TIMING WAVEFORM OF WRITE CYCLE(1) Address CS UB Data in Data Undefined Data out TIMING WAVEFORM OF WRITE CYCLE(2) Address CS UB Data in Data out (WE Controlled CW( WP(1) t AS(3) t High-Z t WHZ (CS Controlled AS(3) CW( WP( High-Z 7 CMOS SRAM ...
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... K6X4016C3F Family TIMING WAVEFORM OF WRITE CYCLE(3) Address CS UB Data in Data out NOTES (WRITE CYCLE wri e occurs during the overlap for single byte operation or simultaneously asserting UB and LB for double byte operation. A write ends at the earliest transi- tion when CS goes high and WE goes high. The t 2 ...
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... K6X4016C3F Family PACKAGE DIMENSIONS 44 PIN THIN SMALL OUTLINE PACKAGE TYPE II (400F) #44 #1 18.81 MAX. 0.741 18.41 0.10 0.725 0.004 0.35 0.805 0. 0.032 0.014 0.004 #23 11.76 0.20 0.463 0.008 #22 1.00 0.10 0.039 0.004 1.20 MAX. 0.047 0.10 MAX 0.004 0.80 0.0315 9 CMOS SRAM Units: millimeter(inch) 0~8 0. 0.010 0.45 ~0.75 0.018 ~ 0.030 0. 0.020 Revision 1.0 September 2003 ...