u3745bm ATMEL Corporation, u3745bm Datasheet
u3745bm
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u3745bm Summary of contents
Page 1
... Power Management (Polling) is also Possible by Means of a Separate Pin via the Microcontroller Description The U3745BM is a multi-chip PLL receiver device supplied in an SO20 package. It has been specially developed for the demands of RF low-cost data transmission systems with low data rates from 1 kBaud to 10 kBaud in Manchester or Bi-phase code. The receiver is well suited to operate with Atmel’ ...
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... Figure 1. Pinning SO20 1 NC ASK 2 CDEM 3 AVCC 4 AGND 5 DGND 6 MIXVCC 7 LNAGND 8 LNA_IN UHF ASK Remote control receiver Data Demod. 1...3 interface IF Amp PLL XTO LNA VCO DATA 20 ENABLE 19 TEST 18 17 POUT MODE 16 U3745BM DVCC 15 XTO 14 LFGND LFVCC 11 µC 4663A–RKE–06/03 ...
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... Selecting 433.92 MHz/315 MHz. Low: 4.90625 MHz (USA), High: 6.76438 (Europe) 17 POUT Programmable output port 18 TEST Test pin, during operation at GND 19 ENABLE Enables the polling mode. Low: polling mode off (sleep mode). High: polling mode on (active mode) 20 DATA Data output/configuration input 4663A–RKE–06/03 U3745BM 3 ...
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... Block Diagram ASK CDEM AVCC AGND DGND MIXVCC LNAGND LNA_IN U3745BM 4 DEMOD_OUT Demodulator and data filter RSSI Limiter out Sensitivity IF Amp reduction th 4 Order Standby logic LPF 3 MHz IF Amp VCO LPF 3 MHz f LNA ¸ DATA ENABLE Polling circuit TEST ...
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... LF can be calculated using the following formula: XTO 820 4.7 nF C10 = C10 S C9 cannot settle in time before the bit check LO and the IF frequency f RF U3745BM is dependent and XTO using the follow ...
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... LNA_IN. The input impedance of that pin is provided in the electrical parame- ters. The parasitic board inductances and capacitances also influence the input matching. The RF receiver U3745BM exhibits its highest sensitivity at the best signal-to- noise ratio in the LNA. Hence, noise matching is the best choice for designing the trans- formation network ...
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... LNAGND U3745BM LNA_IN 25n 47p C16 100p 315 MHz 47n RF L2 TOKO LL2012 RF IN F82NJ 1 B3551 IN 82n 2 IN_GND C2 CASE_GND 10p 3,4 7,8 8 LNAGND U3745BM 9 LNA_IN 25n 33p 3.3p 100p 39n TOKO LL2012 F39NJ U3745BM C17 22p TOKO LL2012 F47NJ 5 OUT 6 OUT_GND 7 ...
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... MHz is used. For other RF input frequencies, refer to Table 1 to determine RF the center frequency. The receiver U3745BM employs an IF bandwidth of B together with the U2745B. SAW transmitters exhibit much higher transmit frequency tol- erances compared to PLL transmitters. Generally necessary to use B together with such transmitters ...
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... Receiving Characteristics 4663A–RKE–06/03 The U3745BM is designed to operate with data coding where the DC level of the data signal is 50%. This is valid for Manchester and Bi-phase coding. If other modulation schemes are used, the DC level should always remain within the range of V and V = 66% ...
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... Polling Circuit and Control Logic Basic Clock Cycle of the Digital Circuitry U3745BM 10 The receiver is designed to consume less than 1 mA while being sensitive to signals from a corresponding transmitter. This is achieved via the polling circuit. This circuit enables the signal path periodically for a short time. During this time the bit check logic verifies the presence of a valid transmitter signal ...
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... T T XClk Clk = I . During the start-up period Soff Startup ) + T Bitcheck and the startup time of a connected microcontroller + T Start_ about XSleep Sleep resulting in a different mode of action as described U3745BM is defined XClk , Startup . Bitcheck and T the Bitcheck ) to Bitcheck . It is Clk 11 ...
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... ENABLE SON OFF command U3745BM 12 XSleep = 1 implies the temporary extension factor. The extended sleep time is used Temp as long as every bit check is OK. If the bit check fails once, this bit is set back to 0 auto- matically resulting in a regular sleep time. This functionality can be used to save current in presence of a modulated disturber similar to an expected transmitter signal ...
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... Receiving mode is set to a lower value. In polling mode, the bit Bitcheck . Figure 8 shows an example where 3 bits are Bitcheck is in between the lower bit check limit T is smaller than T ee 1/f Sig Lim_min T Lim_max U3745BM and the Lim_min or Lim_min and Lim_min . Using ee 13 ...
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... Bit check Counter 0 Figure 11. Timing Diagram for Failed Bit Check (Condition: CV_Lim < Lim_min) ( Lim_min = 14, Lim_max = 24 ) Enable IC Bit check Dem_out Bit check Counter 0 Startup Mode U3745BM 14 = Lim_min ´ Lim_min XClk = (Lim_max –1) ´ Lim_max XClk Lim_min and Lim_max are defined by a 5-bit word each within the LIMIT register. ...
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... Bitcheck requiring a higher value for the transmitter Bitcheck Bitcheck . XClk is to some extent affected by the pre- DATA_min as illustrated in Figure 14 DATA_min DATA_L_max U3745BM 0 varies for Bitcheck . A higher Clk Bitcheck , the receiver of the Data between the = tmin2 is the . This function ...
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... Figure 15. Steady L State Limited DATA Output Pattern after Transmission Enable IC Bit check Dem_out DATA Sleep Mode Switching the Receiver Back to Sleep Mode U3745BM tmin1 CV_Lim < Lim_min or CV_Lim ³ Lim_max t ee Bit check Mode Receiving Mode After the end of a data transmission, the receiver remains active and random noise pulses appear at pin DATA ...
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... Doze Sleep toff The U3745BM receiver is configured via two 12-bit RAM registers called OPMODE and LIMIT. The registers can be programmed by means of the bi-directional DATA port. If the register contents have changed due to a voltage drop, this condition is indicated by a certain output pattern called reset marker (RM). The receiver must be reprogrammed in that case ...
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... Table 4. Effect of the Configuration Word BR_Range BR_Range Baud1 Baud0 U3745BM 18 Table 2. Effect of Bit 1 and Bit 2 in Programming the Registers Bit 1 Bit 2 Action 1 x The receiver is set back to polling mode (OFF command The OPMODE register is programmed 0 0 The LIMIT register is programmed Table 4 and the following illustrate the effect of the individual configuration words ...
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... Sleep ´ Xsleep ´ 1024 ´ T Sleep » 2ms for XSleep = 1 in US-/European applications 22.96 ms, Europe 23.31 ms) (Default) Sleep Sleep . . . (Permanent sleep mode) = Sleep ´ Xsleep ´ 1024 ´ T Sleep 1 (Default) 8 (XSleep is set permanently) 8 (XSleep is set permanently) U3745BM ) Clk ) Clk 19 ...
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... The U3745BM has an integrated power-on reset and brown-out detection circuitry to provide a mechanism to preserve the RAM register information. According to Figure 18, a power-on reset (POR) is generated if the supply voltage V drops below the threshold voltage V the configuration registers in that condition. Once V celed after the minimum reset period t voltage of the receiver is turned on ...
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... Figure 18. Generation of the Power-on Reset V S POR DATA (U3745BM) X Figure 19. Timing of the Register Programming t1 Out1 (mC) DATA (U3745BM) X Serial bi-directional X data line Receiver on Programming the Configuration Register 4663A–RKE–06/03 • If the receiver is set back to polling mode via pin DATA, RM cannot be canceled by accident applied according to the proposal in the section “ ...
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... U3745BM Internal pull-up resistor DATA (U3745BM) To start programming, the serial data line DATA is pulled to ‘L’ for the time period t1 by the microcontroller. When DATA has been released, the receiver becomes the master device. When the programming delay period t2 has elapsed, it emits 14 subsequent synchronization pulses with the pulse length t3 ...
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... Input matched according to Figure 4, BER £ ASK mode For best LO noise (design parameter 820 4.7 nF C10 = 1 nF The capacitive load at pin LF is limited if bit check is used. The limitation therefore also applies to self polling. U3745BM Min. Max. 6 450 150 -55 +125 -40 +85 10 Value 100 = 315 MHz, unless otherwise specified ...
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... Recommended CDEM for best performance Maximum edge-to-edge time period of the input data signal for full sensitivity Minimum edge-to-edge time period of the input data signal for full sensitivity U3745BM ° 433.92 MHz and f amb ...
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... T ´ 2.0 1 ´ Sleep Sleep ´ Sleep Sleep ´ 1024 1024 2.0383 1827 896.5 1045 512.5 1045 512.5 653 320.5 ´ T U3745BM Max. Unit 3. 2.5 µ 540 pF 0 0.2 ´ 0.2 ´ 0.2 ´ Max ...
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... BR_Range0 period at BR_Range1 T DATA_L_max DATA BR_Range2 (Figure 15) BR_Range3 OFF command at Pin ENABLE (Figure 17) Configuration of the Receiver Frequency of the reset marker (Figure 18) U3745BM ° 433.92 MHz and f amb 6.76438-Mhz Osc. (Mode 1) Min. Typ. Max. Min. 0.45 0.24 Bitcheck ...
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... T 129 256 ´ T 522 512 ´ T 1044 64 ´ T 521 Clk 128 ´ T 261 258 ´ T 526 449.5 ´ T 916 U3745BM Max. Unit 1535 ´ µs T Clk 1535 ´ T Clk 1535 ´ T Clk 1535 ´ T Clk ´ 385.5 µ ...
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... Ordering Information Extended Type Number U3745BM-MFL U3745BM-MFLG3 Package Information Package SO20 Dimensions in mm 0.4 1. U3745BM 28 Package Remarks SO20 Tube SO20 Taped and reeled 12.95 12.70 2.35 0.25 0.10 11. 9.15 8.65 7.5 7.3 0.25 10.50 10.20 technical drawings according to DIN specifications 4663A–RKE–06/03 ...
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... Atmel Corporation 2003. Atmel Corporation makes no warranty for the use of its products, other than those expressly contained in the Company’s standard warranty which is detailed in Atmel’s Terms and Conditions located on the Company’s web site. The Company assumes no responsibility for any errors which may appear in this document, reserves the right to change devices or specifications detailed herein at any time without notice, and does not make any commitment to update the information contained herein ...