u3742bm ATMEL Corporation, u3742bm Datasheet

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u3742bm

Manufacturer Part Number
u3742bm
Description
Uhf Ask/fsk Receiver
Manufacturer
ATMEL Corporation
Datasheet

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U3742BM
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MAXIM
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Features
Description
The U3742BM is a multi-chip PLL receiver device supplied in an SO20 package. It has
been especially developed for the demands of RF low-cost data transmission systems
with data rates from 1 kBaud to 10 kBaud (1 kBaud to 3.2 kBaud for FSK) in Manches-
ter or Bi-phase code. The receiver is well suited to operate with Atmel's PLL RF
transmitter IC U2741B. Its main applications in the area of wireless control are teleme-
tering, security technology, tire-pressure monitoring and keyless-entry systems. It can
be used in the frequency receiving range of f
data transmission. All the statements made in this data sheet refer both to
433.92 MHz and 315 MHz applications.
IC Distinguishes the Signal Strength of Several Transmitters via RSSI (Received Signal
Strength Indicator) Output
Minimal External Circuitry Requirements, No RF Components on the PC Board Except
Matching to the Receiver Antenna
High Sensitivity, Especially at Low Data Rates
Sensitivity Reduction Possible Even While Receiving
Fully Integrated VCO
Low Power Consumption Due to Configurable Self-polling with a Programmable Time
Frame Check
Supply Voltage 4.5 V to 5.5 V
Single-ended RF Input for Easy Adaptation to λ/4 Antenna or Printed Antenna on PCB
Operating Temperature Range -40°C to 105°C
Low-cost Solution Due to High Integration Level
ESD Protection According to MIL-STD. 883 (4 KV HBM)
High Image Frequency Suppression Due to 1 MHz IF in Conjunction with a SAW
Front-end Filter (Up to 40 dB Achievable with Newer SAWs)
Communication to Microcontroller Possible via a Single, Bi-directional Data Line
Power Management (Polling) is also Possible by Means of a Separate Pin via the
Microcontroller
0
= 300 MHz to 450 MHz for ASK or FSK
UHF ASK/FSK
Receiver
U3742BM
Rev. 4735A–RKE–11/03

Related parts for u3742bm

u3742bm Summary of contents

Page 1

... Power Management (Polling) is also Possible by Means of a Separate Pin via the Microcontroller Description The U3742BM is a multi-chip PLL receiver device supplied in an SO20 package. It has been especially developed for the demands of RF low-cost data transmission systems with data rates from 1 kBaud to 10 kBaud (1 kBaud to 3.2 kBaud for FSK) in Manches- ter or Bi-phase code ...

Page 2

... Encoder ATARx9x Keys XTO Figure 2. Block Diagram FSK/ASK CDEM RSSI SENS AVCC AGND DGND MIXVCC LNAGND LNA_IN U3742BM 2 U3742BM PLL Antenna Antenna VCO Power LNA amp. FSK/ASK- Dem_out Demodulator and data filter RSSI Limiter out Sensitivity Polling circuit IF Amp reduction control logic 4 ...

Page 3

... Ground VCO 14 XTO Crystal oscillator 15 DVCC Digital power supply 4735A–RKE–11/ SENS 19 2 FSK/ASK 18 3 CDEM 17 4 AVCC 16 5 AGND DGND 15 6 MIXVCC LNAGND LNA_IN U3742BM DATA ENABLE TEST RSSI MODE DVCC XTO LFGND LF LFVCC 3 ...

Page 4

... XTO must be considered. Figure 4. PLL Peripherals U3742BM 4 is divided by a factor of 64. The divided frequency is compared LO by the phase frequency detector. The current output of the phase frequency XTO for the VCO ...

Page 5

... LNA_IN. The input impedance of that pin is provided in the electrical parame- ters. The parasitic board inductances and capacitances also influence the input matching. The RF receiver U3742BM exhibits its highest sensitivity at the best signal-to- noise ratio in the LNA. Hence, noise matching is the best choice for designing the trans- formation network ...

Page 6

... LNAGND U3742BM 9 L LNA_IN 25n 22p 100p L 3 TOKO LL2012 47n F47NJ L 2 F82NJ 5 1 B3551 IN OUT 82n 6 2 OUT_GND IN_GND CASE_GND LNAGND U3742BM 9 LNA_IN 25n 100p 39n TOKO LL2012 F39NJ 4735A–RKE–11/03 ...

Page 7

... MHz is used. For other RF input frequencies, refer to Table 1 on page determine the center frequency. The receiver U3742BM - M3 employs an IF bandwidth of B together with the U2741B in FSK and ASK mode. The subsequent RSSI amplifier enhances the output signal of the IF amplifier before it is fed into the demodulator ...

Page 8

... If the receiver is already active, the data stream at pin DATA will disappear when the input signal is lower than defined by the reduced sensitivity. Instead of the data stream, the pattern according to Figure 9 on page 9 is issued at pin DATA to indi- cate that the receiver is still active. U3742BM Ig(V ) LNA_IN 50k I U3742BM 1.6 1.5 1.4 1.3 1.2 1.1 1.0 -40°C 0.9 25°C ...

Page 9

... Receiver” on page 19). BR_Range must be set in accordance to the used baud rate. The U3742BM is designed to operate with data coding where the DC level of the data signal is 50%. This is valid for Manchester and Bi-phase coding. If other modulation schemes are used, the DC level should always remain within the range of V and V = 66% ...

Page 10

... Receiving The RF receiver U3742BM can be operated with and without a SAW front-end filter typical automotive application, a SAW filter is used to achieve better selectivity. The Characteristics selectivity with and without a SAW front-end filter is illustrated in Figure 10. This exam- ple relates to ASK mode. FSK mode exhibits similar behavior. Note that the mirror frequency is reduced ...

Page 11

... Other applications (T is dependent on f Clk The electrical characteristic is given as a function of T BR_Range0: T XClk BR_Range1: T XClk BR_Range2: T XClk BR_Range3: T XClk U3742BM is derived from the crystal oscillator Clk ) which also defines the RFin ). LO MODE L : USA(:10 Europe(:14) DVCC 15 XTO Clk ...

Page 12

... According to Table 7 on page 21, the highest register value of Sleep sets the receiver into a permanent sleep condition. The receiver remains in that condition until another value for Sleep is programmed into the OPMODE register. This function is desirable where several devices share a single data line. U3742BM 12 while consuming low current of I Sleep , all signal processing circuits are enabled and settled ...

Page 13

... Lim_min XClk = (Lim_max - 1) ´ T Lim_max XClk , T and T Lim_min Lim_max XClk The minimum edge-to-edge time t Lim_max XClk U3742BM is in between the lower bit check limit T is smaller than ee 1/f Sig . The time resolution when defining DATA_L_min DATA_H_min and Lim_min ...

Page 14

... The receiver is turned on permanently and passes the data stream to the connected microcontroller. It can be set to Sleep mode through an OFF command via pin DATA or ENABLE Son OFF command U3742BM 14 Sleep: 5-bit word defined by Sleep0 to Sleep4 in OPMODE register X : Extension factor defined by Sleep XSleep ...

Page 15

... Bit check failed (CV_Lim < Lim_min) 1/2 Bit 1112 Bit check mode U3742BM 1/2 Bit 1/2 Bit Receiving mode Bit check ok Bit check ok 1/2 Bit 151617 1011121314 Sleep mode 1/2 Bit ...

Page 16

... This processing depends on the selected baud rate range (BR_Range). Figure 18 on page 17 illustrates how Dem_out is synchronized by the extended clock cycle T the bit check counter. Data can change its state only after T edge-to-edge time period U3742BM 16 1/2 Bit 10 1112 13141516171819 ...

Page 17

... DATA_L_max t ee tmin1 CV_Lim < Lim_min or CV_Lim ≥ Lim_max t ee Bit check mode Receiving mode U3742BM is to some extent affected by the pre- DATA_min is in between the ee = tmin2 is DATA_min . This function DATA_L_max tmin2 t ...

Page 18

... ENABLE is held to 'L'. If the receiver is polled exclusively by a micro- controller, T command is the faster option than via pin DATA at the cost of an additional connection to the microcontroller. Figure 21. Timing Diagram of the OFF-command via Pin DATA t 1 Out1 (microcontroller) DATA (U3742BM) X Serial bi-directional X data line Receiving mode U3742BM ...

Page 19

... Receiving mode Configuration of the The U3742BM receiver is configured via two 12-bit RAM registers called OPMODE and LIMIT. The registers can be programmed by means of the bi-directional DATA port. If Receiver the register contents have changed due to a voltage drop, this condition is indicated by a certain output pattern called reset marker (RM) ...

Page 20

... Baud0 Table 5. Effect of the Configuration Word N N Bitcheck BitChk1 Table 6. Effect of the Configuration Bit Reserved Reserved Bit 0 1 U3742BM 20 Bit 6 Bit 7 Bit 8 Bit 9 V Bitcheck POUT BitChk0 POUT Sleep4 Sleep3 Baud Rate Range/Extension Factor for Bit Check Limits (XLim) BR_Range0 (application USA/Europe: BR_Range0 = 1 ...

Page 21

... U3742BM = Sleep × Xsleep × 1024 × T Start Value for Sleep Counter (T ) Sleep Clk 22.96 ms, Europe 23.31 ms) (Default) Sleep . . . (Permanent sleep mode) = Sleep × Xsleep × 1024 × T Sleep 1 (Default) 8 (XSleep is set permanently) ...

Page 22

... Conservation of the Register The U3742BM has an integrated power-on reset (POR) and brown-out detection cir- Information cuitry to provide a mechanism to preserve the RAM register information. According to Figure 23, a power-on reset is generated if the supply voltage V below the threshold voltage V configuration registers in that condition. Once V after the minimum reset period t the receiver is turned on ...

Page 23

... Figure 24. Timing of the Register Programming t 1 Out1 (microcontroller) DATA (U3742BM) X Serial bi-directional X data line Receiving mode Programming the The configuration registers are programmed serially via the bi-directional data line Configuration Register according to Figure 24 and Figure 25. Figure 25. One-wire Connection to a Microcontroller To start programming, the serial data line DATA is pulled to 'L' for the time period t the microcontroller ...

Page 24

... Parameters Power dissipation Junction temperature Storage temperature Ambient temperature Maximum input level, input matched Thermal Resistance Parameters Junction ambient U3742BM 24 initiates the programming of the configuration registers. 1 < 1535 ´ (min) < (min) is the minimum specified value for the relevant ...

Page 25

... Sig Sig Sig 6/f 6.5/f 6/f Sig Sig Sig 9/f 9.5/f 9/f Sig Sig Sig IF 1.0 1.0 1.8 1.0 1.8 3.2 1.8 3.2 5.6 3.2 5.6 10.0 5.6 149 182 75 91 37.3 45.5 18.6 22.8 U3742BM = 433.92 MHz and f = 315 MHz, unless other (Mode 0) Variable Oscillator Typ. Max. Min. Typ. 2.0383 1/(f /10) XTO 1/(f /14) XTO ´ 16 ´ Clk 8 ´ Clk 4 ´ Clk 2 Clk ´ ...

Page 26

... Delay until the program window starts t (Figure 21, Figure 24) Programming window t (Figure 21, Figure 24) Time frame of a bit t (Figure 24) Programming pulse (Figure t 21, Figure 24) U3742BM 6.76438 Mhz Oscillator 4.90625 Mhz Oscillator (Mode 1) Min. Typ. Max. Min. 2169 1085 542 271 3.1 3.05 117.9 2188 ...

Page 27

... RF in Input matched according to Figure 6, BER £ ASK mode f = 432.92 MHz osc at 1 MHz at 10 MHz at ±f XTO U3742BM = 433.92 MHz and f = 315 MHz, unless other (Mode 0) Variable Oscillator Typ. Max. Min. Typ. 128 ´ T 261 Clk 258 ´ T ...

Page 28

... amb S Sensitivity variation ASK for full operating range including IF filter = 25 ° compared amb S Input sensitivity FSK Input sensitivity FSK U3742BM Test Conditions For best LO noise (design parameter) = 820 4 ...

Page 29

... BR_Range0 (Default) BR_Range1 BR_Range2 BR_Range3 BR_Range0 (Default) BR_Range1 BR_Range2 BR_Range3 R connected from pin Sens Sense S input matched according to Figure 6 U3742BM = 433.92 MHz and f = 315 MHz, unless other Symbol Min. Typ. Max +2.5 -1.5 Ref D P +5.5 -1 ...

Page 30

... FSK/ASK input - Low-level input voltage - High-level input voltage ENABLE input - Low-level input voltage - High-level input voltage MODE input - Low-level input voltage - High-level input voltage TEST input - Low-level input voltage U3742BM Test Conditions = 25 ° amb = 433 ...

Page 31

... Ordering Information Extended Type Number U3742BM-M3FL U3742BM-M3FLG3 Package Information Package SO20 Dimensions in mm 0.4 1. 4735A–RKE–11/03 Package Remarks SO20 Tube SO20 Taped and reeled 12.95 12.70 2.35 0.25 0.10 11.43 11 technical drawings according to DIN specifications 10 U3742BM 9.15 8.65 7.5 7.3 0.25 10.50 10.20 31 ...

Page 32

... Fax: (81) 3-3523-7581 Disclaimer: Atmel Corporation makes no warranty for the use of its products, other than those expressly contained in the Company’s standard warranty which is detailed in Atmel’s Terms and Conditions located on the Company’s web site. The Company assumes no responsibility for any errors which may appear in this document, reserves the right to change devices or specifications detailed herein at any time without notice, and does not make any commitment to update the information contained herein ...

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