h5ps1g83nfr Hynix Semiconductor, h5ps1g83nfr Datasheet
h5ps1g83nfr
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h5ps1g83nfr Summary of contents
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... DDR2 SDRAM This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any responsibility for use of circuits described. No patent licenses are implied. Rev. 0.1 / Feb. 2010 H5PS1G83NFR H5PS1G83NFR 1 ...
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... Revision Details Rev. 0.1 Initial data sheet released Rev. 0.1 / Feb. 2010 History H5PS1G83NFR Draft Date Feb. 2010 2 ...
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... Input AC Logic Level 3.2.3 AC Input Test Conditions 3.2.4 Differential Input AC Logic Level 3.2.5 Differential AC Output Parameters 3.3 Output Buffer Levels 3.3.1 Output AC Test Conditions 3.3.2 Output DC Current Drive 3.3.3 OCD default characteristics 3.4 IDD Specifications & Measurement Conditions 3.5 Input/Output Capacitance 4. AC Timing Specifications 5. Package Dimensions Rev. 0.1 / Feb. 2010 H5PS1G83NFR 3 ...
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... JEDEC standard 60ball FBGA(x8) • Full strength driver option controlled by EMR • On Die Termination supported • Off Chip Driver Impedance Adjustment supported • Read Data Strobe supported • Self-Refresh High Temperature Entry Rev. 0.1 / Feb. 2010 H5PS1G83NFR 4 ...
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... Operating Frequency table for complete part number. Hynix lead-free products are compliant to RoHS. 1.1.3 Operating Frequency Grade tCK(ns 2.5 S5 2.5 Rev. 0.1 / Feb. 2010 Configuration Package 60 Ball 128Mx8 CL tRCD H5PS1G83NFR tRP Unit Clk 5 Clk 6 Clk 5 5 ...
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... E VSS F WE CKE G BA1 BA0 H A1 A10 A12 ROW AND COLUMN ADDRESS TABLE ITEMS # of Bank Page size H5PS1G83NFR VSSQ DQS VDDQ DQS VSSQ DQ7 VDDQ DQ0 VDDQ DQ2 VSSQ DQ5 VSSDL CK VDD RAS CK ODT CAS CS A2 ...
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... LDQS/LDQS and UDQS/UDQS "single-ended DQS signals" refers to any of the following with A10 = 1 of EMR(1) x4 DQS x8 DQS x8 DQS, RDQS, x16 LDQS and UDQS H5PS1G83NFR DESCRIPTION has become stable during the power on and initialization if EMR(1)[A11 EMR(1)[A11 EMR(1)[A11 EMR(1)[A11 ...
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... PIN TYPE NC V Supply DDQ VSSQ Supply V Supply DDL V Supply SSDL VDD Supply V Supply SS V Supply REF Rev. 0.1 / Feb. 2010 No Connect: No internal electrical connection is present. DQ Power Supply: 1.8V +/- 0.1V DQ Ground DLL Power Supply: 1.8V +/- 0.1V DLL Ground Power Supply: 1.8V +/- 0.1V Ground Reference voltage. H5PS1G83NFR DESCRIPTION -Continued- 8 ...
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... Operating Temperature is the case surface temperature on the center/top side of the DRAM. For the measure- ment conditions, please refer to JESD51-2 standard 85~95° Double refresh rate(tREFI: 3.9us) is required, and to enter the self refresh mode at this tem- OPER perature range it must be required an EMRS command to change itself refresh rate. Rev. 0.1 / Feb. 2010 H5PS1G83NFR Rating Units - ...
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... V (ac) to test pin separately, then measure current I (ac), and VDDQ values defined in SSTL_18 IL V (ac (ac Rtt(eff) = I(V (ac delta 100% VDDQ H5PS1G83NFR Units Max. 1.9 V 1.9 V 1.9 V 0.51*VDDQ mV VREF+0.04 V MIN NOM MAX UNITS NOTES ohm 120 150 ...
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... Rev. 0.1 / Feb. 2010 Min. VREF + 0.125 - 0.3 DDR2 667,800 Min. VREF + 0.200 - Condition Input reference voltage to V max for falling edges as shown in the figure below. IL(ac) delta max IL(ac) H5PS1G83NFR Max. Units VDDQ + 0.3 V VREF - 0.125 V Units Max. - VREF - 0.200 Value Units 0 DDQ 1 ...
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... VDDQ. VOX(AC) indicates the voltage at which differential output signals must cross. Rev. 0.1 / Feb. 2010 Min. 0.5 0.5 * VDDQ - 0.175 0.5 * VDDQ + 0.175 V DDQ SSQ < Differential signal levels > Min. 0.5 * VDDQ - 0.125 0.5 * VDDQ + 0.125 H5PS1G83NFR Max. Units Notes VDDQ + 0 Crossing point Max. Units Notes V ...
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... V OUT DDQ OH /I must be less than 21 ohm for values of V OUT OL are based on the conditions given in Notes 1 and 2. They are used to test min plus a noise margin and V IH H5PS1G83NFR SSTL_18 Class II Units 0 DDQ SSTl_18 Units - 13.4 mA 13.4 ...
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... DRAM output slew rate specification applies to 400, 533 and 667 MT/s speed bins. 8. Timing skew due to DRAM output slew rate mis-match between DQS / DQS and associated DQs is included in tDQSQ and tQHS specification. Rev. 0.1 / Feb. 2010 Parameter Min - 0 0 Sout 1.5 VTT 25 ohms Reference point H5PS1G83NFR Nom Max Unit Notes - - ohms 1 1.5 ohms 6 4 ohms 1,2,3 ...
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... F IDD3P S IDD3N IDD4W IDD4R IDD5 Normal IDD6 Low power IDD7 Rev. 0.1 / Feb. 2010 DDR2 667 155 150 175 10 5 200 H5PS1G83NFR DDR2 800 Units 180 mA 170 mA 180 ...
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... RCD = 1* t CK(IDD); CKE is HIGH HIGH between valid commands; Address bus inputs are STABLE during DESELECTs; Data pattern is same as IDD4R; - Refer to the following page for detailed timing conditions Rev. 0.1 / Feb. 2010 Conditions Fast PDN Exit MR(12 Slow PDN Exit MR(12 H5PS1G83NFR Units ...
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... SWITCHING is defined as: inputs changing between HIGH and LOW every other clock cycle (once per two clocks) for address and control signals, and inputs changing between HIGH and LOW every other data transfer (once per clock) for DQ signals not including masks or strobes. Rev. 0.1 / Feb. 2010 H5PS1G83NFR 17 ...
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... A0 RA0 D A1 RA1 D A2 RA2 D A3 RA3 RA4 D A5 RA5 D A6 RA6 D A7 RA7 Timing Patterns for 8 bank devices x16 Rev. 0.1 / Feb. 2010 DDR2-800 5-5-5 6-6 12.5 15 57.5 60 7.5 7 2.5 2 70000 70000 12 105 105 127.5 127.5 197.5 197.5 H5PS1G83NFR DDR2-667 5-5-5 Units 5 tCK 7 70000 105 ns 127.5 ns 197 ...
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... Input capacitance delta, all other input-only pins Input/output capacitance, DQ, DM, DQS, DQS Input/output capacitance delta, DQ, DM, DQS, DQS Rev. 0.1 / Feb. 2010 DDR2 667 Symbol Min Max CCK 1.0 2.0 CDCK x 0.25 CI 1.0 2.0 CDI x 0.25 CIO 2.5 3.5 CDIO x 0.5 H5PS1G83NFR DDR2 800 Units Min Max 1.0 2 0.25 pF 1.0 1. 0.25 pF 2 ...
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... Refer to Specific Notes 32. 3. Refer to Specific Notes 3. Rev. 0.1 / Feb. 2010 = 1.8 +/- 0.1V) DD 256Mb 512Mb 1Gb Symbol tRFC 75 0 ℃≤ T ≤ 85℃ 7.8 CASE ≤ 95℃ 3.9 85℃＜ T CASE DDR2-800 min 6-6 H5PS1G83NFR 2Gb 4Gb Units Notes 105 127.5 195 327.5 7.8 7.8 7.8 7.8 3.9 3.9 3.9 3.9 DDR2-667 min min 4-4-4 5-5 ...
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... WR+tnRP - H5PS1G83NFR DDR2-800 Unit min max -400 +400 ps -350 +350 ps 0.48 0.52 tCK(avg) 0.48 0.52 tCK(avg) min(tCL(abs tCH(abs)) 2500 8000 6,7,8,20,28,31 125 - ps 6,7,8,21,28,31 0.6 - tCK(avg) 0.35 - tCK(avg) - tAC max ps tAC min ...
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... H5PS1G83NFR -Continued- DDR2-800 Unit Notes min max 7 24,32 7.5 ns tRFC + 10 ns 200 - nCK 2 - nCK 2 nCK nCK 3 nCK 2 2 ...
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... Output slew rate is characterized under the test conditions as shown below. VDDQ DUT Rev. 0.1 / Feb. 2010 DQ DQS Output DQS RDQS Timing RDQS reference point AC Timing Reference Load DQ Output DQS, DQS RDQS, RDQS Test point Slew Rate Test Load H5PS1G83NFR DDQ Ω DDQ Ω ...
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... D V (ac (ac) IH DMin DMin V (ac) IL Figure -- Data input (write) timing RPRE Q t DQSQmax t QH Figure -- Data output (read) timing H5PS1G83NFR t WPST V (dc (dc (dc) IH DMin DMin V (dc RPST DQSQmax ...
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... H5PS1G83NFR 1.4 V/ns 1.2 V/ns 1.0 V/ns △ △ △ △ △ △ tDH tDS tDH tDS tDH tDS - - - - - - - - - - - - - -59 2 -47 14 -35 26 ...
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... Delta TF V Setup Slew Rate = Falling Signal Rev. 0.1 / Feb. 2010 nominal slew rate Delta TR (dc)-V (ac)max Setup Slew Rate REF IL Rising Signal Delta TF H5PS1G83NFR nominal slew rate REF region V (ac)min-V (dc) REF IH = Delta TR 26 ...
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... Setup Slew Rate Tangent line[V = Falling Signal Rev. 0.1 / Feb. 2010 nominal line Tangent line Delta TR Setup Slew Rate Tangent line[V = Rising Signal (dc)-V (ac)max] REF IL Delta TF H5PS1G83NFR tangent line REF region (ac)min-V (dc)] REF IH Delta TR 27 ...
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... Vss Hold Slew Rate V = Rising Signal Rev. 0.1 / Feb. 2010 REF nominal slew rate Delta TR (dc)-V (dc)max Hold Slew Rate REF IL Falling Signal Delta TR H5PS1G83NFR nominal slew rate Delta TF V (dc)min - V (dc) IH REF = Delta TF 28 ...
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... Hold Slew Rate Tangent line[V = Rising Signal Rev. 0.1 / Feb. 2010 Tangent nominal line line Delta TR (dc)-V (ac)max] REF IL Delta TR Hold Slew Rate = Falling Signal H5PS1G83NFR nominal line tangent line Delta TF Tangent line[V (ac)min-V REF IH Delta TF (dc)] 29 ...
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... Hold(tIH) nominal slew rate for a falling signal is defined as the REF (dc). If the actual signal is always later than the nominal slew rate REF (dc) region’, use nominal slew rate for derating value(see Fig.c) If the actual H5PS1G83NFR 1.0 V/ns △ tIS △ tIH Uni ts ...
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... The actual voltage measure- ment points are not critical as long as the calculation is consistent. 19. tRPST end point and tRPRE begin point are not referenced to a specific voltage level but specify when the Rev. 0.1 / Feb. 2010 H5PS1G83NFR 31 ...
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... VOH + 2xmV VTT + xmV VOL + 1xmV VTT -xmV VOL + 2xmV VTT - 2xmV tLZ , tRPRE begin point = 2*T1-T2 (ac) level to the differential data strobe crosspoint for a falling signal IL Differential Input waveform timing tDS tDH tDS H5PS1G83NFR tLZ tRPRE begin point T1 T2 tDH V DDQ V min IH(ac) V min ...
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... For example, the device will support tnRP = RU {tRP / tCK (avg)}, which is in clock cycles, if all input clock jitter specifications are met. This means: For DDR2-667 5-5-5, of which tRP = 15ns, the device will support Rev. 0.1 / Feb. 2010 H5PS1G83NFR (dc) level for a rising sig ...
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... H5PS1G83NFR DDR2-800 Units Notes min max -100 100 -200 200 ps 35 -160 160 ps 35 ...
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... CK (avg), min + tCH (abs) tJIT (per), min tCL (avg), min* tCK (avg), min + tCL (abs) tJIT (per), min H5PS1G83NFR max Units tCK (avg), max + tJIT (per), max tCH (avg), max* tCK (avg), max + tJIT(per), max tCL (avg), max* tCK (avg), max + ...
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... HIGH pulse width of 0.5 relative to tCK (avg). tAOF, min and tAOF, max should each be derated by the same amount as the actual amount of tCH (avg) offset present at the DRAM input with respect to 0.5. For example input clock has a worst case tCH (avg) of 0.48, the tAOF, min should be derated by sub- Rev. 0.1 / Feb. 2010 H5PS1G83NFR 36 ...
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... Thus the final derated values for tAOF are; tAOF, min (derated_final) = tAOF, min (derated tJIT (duty), max - tERR(6-10per),max} tAOF, max (derated_final) = tAOF, max (derated tJIT (duty), min - tERR(6-10per),min} Rev. 0.1 / Feb. 2010 H5PS1G83NFR 37 ...
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... Fine Pitch Ball Grid Array Outline 8.00 ± 0.10 A1 BALL MARK < Top View> 60X Φ0.45 ± 0.05 < Bottom View> Rev. 0.1 / Feb. 2010 2.10 ± 0.10 A1 BALL MARK 1.60 1.60 0.80 Note: All dimensions are in millimeters. H5PS1G83NFR 2-R0.13MAX < SIDE View> 1.10 ± 0.10 0.34 ± 0.05 38 ...