gal6001 Lattice Semiconductor Corp., gal6001 Datasheet

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gal6001

Manufacturer Part Number
gal6001
Description
High Performance E2 Cmos Fpla Generic Array Logic?
Manufacturer
Lattice Semiconductor Corp.
Datasheet

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0
• HIGH PERFORMANCE E
• LOW POWER CMOS
• E
• UNPRECEDENTED FUNCTIONAL DENSITY
• HIGH-LEVEL DESIGN FLEXIBILITY
• APPLICATIONS INCLUDE:
Using a high performance E
Semiconductor has produced a next-generation programmable
logic device, the GAL6001. Having an FPLA architecture, known
for its superior flexibility in state-machine design, the GAL6001
offers a high degree of functional integration and flexibility in a 24-
pin, 300-mil package.
The GAL6001 has 10 programmable Output Logic Macrocells
(OLMC) and 8 programmable Buried Logic Macrocells (BLMC). In
addition, there are 10 Input Logic Macrocells (ILMC) and 10
I/O Logic Macrocells (IOLMC). Two clock inputs are provided for
independent control of the input and output macrocells.
Advanced features that simplify programming and reduce test time,
coupled with E
programmability, and functionality testing of each GAL6001 during
manufacture. As a result, Lattice Semiconductor delivers 100% field
programmability and functionality of all GAL products. In addition,
100 erase/write cycles and data retention in excess of 20 years are
specified.
Copyright © 1997 Lattice Semiconductor Corp. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject
to change without notice.
LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A.
Tel. (503) 268-8000; 1-800-LATTICE; FAX (503) 268-8556; http://www.latticesemi.com
6001_02
Features
Description
— 30ns Maximum Propagation Delay
— 27MHz Maximum Frequency
— 12ns Maximum Clock to Output Delay
— TTL Compatible 16mA Outputs
— UltraMOS
— 90mA Typical Icc
— Reconfigurable Logic
— Reprogrammable Cells
— 100% Tested/100% Yields
— High Speed Electrical Erasure (<100ms)
— 20 Year Data Retention
— 78 x 64 x 36 FPLA Architecture
— 10 Output Logic Macrocells
— 8 Buried Logic Macrocells
— 20 Input and I/O Logic Macrocells
— Asynchronous or Synchronous Clocking
— Separate State Register and Input Clock Pins
— Functional Superset of Existing 24-pin PAL
— Sequencers
— State Machine Control
— Multiple PLD Device Integration
2
CELL TECHNOLOGY
and FPLA Devices
2
CMOS reprogrammable cells, enable 100% AC, DC,
®
Advanced CMOS Technology
2
CMOS
2
CMOS technology, Lattice
®
TECHNOLOGY
®
1
Functional Block Diagram
Macrocell Names
Pin Names
Pin Configuration
ILMC
IOLMC I/O LOGIC MACROCELL
BLMC
OLMC
I
ICLK
OCLK
0
NC
- I
INPUTS
2-11
I
I
I
I
I
I
CLOCK
INPUT
10
11
5
7
9
{
12
4
INPUT LOGIC MACROCELL
BURIED LOGIC MACROCELL
OUTPUT LOGIC MACROCELL
INPUT
INPUT CLOCK
OUTPUT CLOCK
GAL6001
Top View
2
11
14
2
ILMC
PLCC
0
7
BLMC
High Performance E
28
ICLK
16
D
E
26
18
25
23
21
19
I/O/Q
I/O/Q
I/O/Q
NC
I/O/Q
I/O/Q
I/O/Q
AND
OR
Generic Array Logic™
I/O/Q
V
GND
CC
GAL6001
D
E
OUTPUT
ENABLE
I/ICLK
14
GND
BIDIRECTIONAL
POWER (+5)
GROUND
23
OLMC
I
I
I
I
I
I
I
I
I
I
OCLK
2
1
6
12
CMOS FPLA
6001
14
DIP
GAL
23
IOLMC
July 1997
18
24
13
{
OUTPUTS
OUTPUT
14 - 23
CLOCK
Vcc
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
OCLK

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gal6001 Summary of contents

Page 1

... Using a high performance E 2 CMOS technology, Lattice Semiconductor has produced a next-generation programmable logic device, the GAL6001. Having an FPLA architecture, known for its superior flexibility in state-machine design, the GAL6001 offers a high degree of functional integration and flexibility in a 24- pin, 300-mil package. The GAL6001 has 10 programmable Output Logic Macrocells (OLMC) and 8 programmable Buried Logic Macrocells (BLMC) ...

Page 2

... GAL6001 Ordering Information Commercial Grade Specifications Part Number Description GAL6001B Device Name Speed (ns Low Power Power ...

Page 3

... Input Logic Macrocell (ILMC) and I/O Logic Macrocell (IOLMC) The GAL6001 features two configurable input sections. The ILMC section corresponds to the dedicated input pins (2-11) and the IOLMC to the I/O pins (14-23). Each input section is configurable as a block for asynchronous, latched, or registered inputs. Pin 1 (ICLK) is used as an enable input for latched macrocells clock input for registered macrocells ...

Page 4

... ILMC (Input Logic Macrocell) JEDEC Fuse Numbers ISYN 8218 LATCH INVALID 0 REG LATCH ILMC/IOLMC Generic Logic Block Diagram IOLMC (I/O Logic Macrocell) JEDEC Fuse Numbers LATCH ISYN 8219 8220 4 Specifications GAL6001 MUX AND ARRAY 0 1 ISYN LATCH 8221 ...

Page 5

... Specifications GAL6001 OE PRODUCT TERM AND IOLMC ARRAY MUX 1 I/O 0 OLMC ONLY BLMC (Buried Logic Macrocell) JEDEC Fuse Numbers OCLK OSYN 8175 8176 8172 8173 8169 8170 ...

Page 6

... GAL6001 Logic Diagram LTC H. Specifications GAL6001 LTCH EG. 6 REG. MUX ...

Page 7

... GAL6001 Logic Diagram (Continued) The number of Differential Product Terms that may switch is limited to a maximum of 15. Refer to the Differential Product Term Switching Applications sec- tion of this data sheet for a full explanation. Specifications GAL6001 7 ...

Page 8

... MAX. Vin = MAX. Vin = 0.5V CC OUT = 0. 3. 15MHz Outputs Open = MAXIMUM Specifications GAL6001 ) ............................... MIN. TYP. 2 MAX. — 0.8 Vss – 0.5 2.0 — Vcc+1 — — -10 — — — — 0.5 IH 2.4 — IH — ...

Page 9

... A Input or I/O to Asynchronous Reg. Reset t arr1 — Asynchronous Reset to OCLK Recovery Time t arr2 — Asynchronous Reset to Sum Term CLK Recovery Time 1) Refer to Switching Test Conditions section. Over Recommended Operating Conditions 9 Specifications GAL6001 COM -30 MIN. MAX. — 30 — 30 — 35 — 35 — 35 — ...

Page 10

... INPUT or I/O FEEDBACK t h4 OCLK t co4 REGISTERED OUTPUT t en INPUT or I/O FEEDBACK DRIVING AR REGISTERED OUTPUT t wl1 Sum Term CLK t wl2 OCLK 10 Specifications GAL6001 VALID INPUT t t su2 h2 t co2 t su5 t su6 Registered Input VALID INPUT t t su3 h3 t co3 f 1/ max Registered Output (OCLK) ...

Page 11

... See Figure FROM OUTPUT (O/Q) UNDER TEST 390 50pF 390 50pF 390 50pF *C 390 5pF 390 5pF 11 Specifications GAL6001 CLK LOGIC ARRAY REGISTER max with Internal Feedback 1/( su+ + INCLUDES TEST FIXTURE AND PROBE CAPACITANCE ...

Page 12

... Then the machine can be sequenced and the outputs tested for correct next state generation. All of the registers in the GAL6001 can be preloaded, including the ILMC, IOLMC, OLMC, and BLMC registers. In addition, the con- tents of the state and output registers can be examined in a special diagnostics mode ...

Page 13

... Q - OUTPUT FEEDBACK/EXTERNAL OUTPUT REGISTER Circuitry within the GAL6001 provides a reset signal to all registers during power-up. All internal registers will have their Q outputs set low after a specified time (tpr MAX result, the state on the registered output pins (if they are enabled) will always be high on power-up, regardless of the programmed polarity of the output pins ...

Page 14

... FALL - Delta Tco vs Output Loading 12 RISE 10 8 FALL 100 150 200 250 300 Output Loading (pF) 14 Specifications GAL6001 Normalized Tsu vs Vcc 1.2 1.1 1 0.9 0.8 5.50 4.50 4.75 5.00 Supply Voltage (V) Normalized Tsu vs Temp 1.4 1.3 PT H->L 1.2 PT L->H 1.1 1 0.9 0.8 0.7 125 -55 - Temperature (deg. C) Delta Tco Outputs ...

Page 15

... Vin (V) Voh vs Ioh 0.00 10.00 20.00 30.00 40.00 50.00 60.00 Ioh(mA) Normalized Icc vs Temp 1.2 1.1 1 0.9 0.8 0.7 5.50 -55 - 100 Temperature (deg. C) Input Clamp (Vik 100 -2.00 -1.50 -1.00 -0.50 Vik (V) 15 Specifications GAL6001 Voh vs Ioh 4.5 4.25 4 3.75 3.5 0.00 1.00 2.00 3.00 Ioh(mA) Normalized Icc vs Freq. 1.20 1.10 1.00 0.90 0.80 125 Frequency (MHz) 0.00 4.00 100 ...

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