cx29600 Mindspeed Technologies, cx29600 Datasheet

cx29600

Manufacturer Part Number

cx29600

Description

Optiphytm - M155 Sts-3 Sonet/sdh Multiplexer

Manufacturer

Mindspeed Technologies

Datasheet

1.CX29600.pdf (219 pages)

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CX29600

OptiPHY

multiplexer/demultiplexer functions for a single STS-3/STM-1 data stream. All mappings are

compliant with SONET/SDH standards including Bellcore GR-253, ANSI T1.105, and ITU G.707.

section, line, and path layers, framing, scrambling/descrambling, alarm detection/insertion, and

BIP error monitoring. Serial interfaces for Section and Line DCC's are also provided. Automatic

Protection Switching (APS) is supported via full K1/K2 byte access with Bit Error Rate (BER)

calculations done in hardware. This APS support is also fully compatible with Mindspeed’s APS

protocol stack software package.

The drop-side interface is a byte-wide data and clock interface for STS-3 streams in Mindspeed's

SONET Interleave interface (SI-Bus) format. This interface provides the ability to pass payload

information to nearby processing elements in either STS-1, VC-4 or VC-3 format. An additional

serial data channel is provided to support downstream processing (i.e., HDLC). -Continued-

Functional Block Diagram

29600-DSH-001-B

LRxData +/-

LTxData +/-

CX29600 is a highly integrated, single-port chip that provides SONET/SDH processing and

The CX29600 supports full-duplex overhead processing of SONET/SDH data streams for

The line-side interface is compliant with industry standard LVPECL serial interface transceivers.

LSigDet

PECL

Transmit Clock

Synthesizer

- M155 STS-3 SONET/SDH Multiplexer

CDR

Parallel

Serial

Microprocessor

Interface

RX Framer

TX Framer

(STM-1)

STS-3

Section/Line

Interface

DCC

SOH/LOH

SOH/

LOH

insert

Processor

Pointer

insert

POH

Section/Line

Orderwire

Interface

POH

Distinguishing Features

• Processes combinations of

• Glueless connectivity to the

• Automatic Protection

• Device Driver reference source

• Generates/terminates section,

–

STS-3 payload

framing/multiplexing for:

– 1x STS-3/STM-1

CX29503 and

CX28500/CX28560 devices.

Switching

– Bit Error Rate calculations

– User-programmable signal

code available

line, and path overhead.

Interface

SI-BUS

JTAG

performed in hardware

fail and signal degrade

thresholds

SRxData[7:0]

STxData[7:0]

–Continued–

June 2005

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