cn8237 Mindspeed Technologies, cn8237 Datasheet

cn8237

Manufacturer Part Number

cn8237

Description

Atm Oc-12 Servicesar Plus With Xbr Traffic Management

Manufacturer

Mindspeed Technologies

Datasheet

1.CN8237.pdf (415 pages)

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CN8237

ATM OC-12 ServiceSAR Plus with xBR Traffic Management

The CN8237 Service Segmentation and Reassembly (ServiceSAR) Controller integrates ATM

terminal functions, PCI Bus Master and Slave controllers, and a UTOPIA 1 or 2 interface with

service-specific functions in a single package for AAL0 and AAL5 operations. The ServiceSAR

Controller generates and terminates ATM traffic and automatically schedules cells for

transmission. The CN8237 is targeted at 622 Mbps throughput systems where the number of

VCCs is relatively large, or the performance of the overall system is critical. Networking

equipment it supports ranges from routers and Ethernet switches to ATM Edge switches and

Frame Relay switches.

Service-Specific Performance Accelerators

The CN8237 incorporates numerous service-specific features designed to accelerate and

enhance system performance. For instance, the CN8237 implements Echo Suppression of LAN

traffic via LECID filtering and supports Frame Relay DE to CLP interworking.

Advanced xBR Traffic Management

The xBR Traffic Manager in the CN8237 supports multiple ATM service categories. Categories

include CBR, VBR (both single and dual leaky bucket), UBR, GFR (Guaranteed Frame Rate),

and ABR (explicit rate, relative rate, or EFCI marking). The CN8237 manages each VCC

independently. It dynamically schedules segmentation traffic to comply with up to 16+ CBR

user-configured scheduling priorities for the various traffic classes. Scheduling control is

based on a user-specified time reference. ABR channels are managed in hardware according

to user-programmable ABR templates. These templates tune the performance of the CN8237’s

ABR algorithms to a specific system’s or network’s requirements (user-defined granularity).

–Continued–

Functional Block Diagram

Data Sheet

Multi-client

PCI Bus

Master/

Slave

PCI

Counters

Timer

Proc'r

DMA

Co-

Memory Interface

Segmentation

Local RSM

Coprocessor

CBR, VBR, ABR,

Local SEG

Coprocessor

Reassembly

UBR, GFR

RSM Local

Memory Bus

SEG Local

Memory Bus

Traffic Manager

Control/

Status

FIFO

Cell

CN8237

Patent Nos. 5,949,781

UTOPIA

Master/

Slave

RX/TX

PHY Interface

5,768,275

5,889,779

CX29704

Device

PHY

Distinguishing Features

Service-Specific Performance

Accelerators

• LECID filtering and echo

• Dual leaky bucket based on

• Frame relay DE interworking

• Internal SNMP MIB counters

• IP over ATM; supports both

Flexible Architectures

• Multi-peer host

• Direct switch attachment via

• ATM terminal

LIU

suppression

CLP (frame relay)

CLP0+1 and ABR shaping

reverse UTOPIA

– Host control

– Local bus control

28237-DSH-001-C

August 2003

–Continued–

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