m28529-12 Mindspeed Technologies, m28529-12 Datasheet

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m28529-12

Manufacturer Part Number
m28529-12
Description
Inverse Multiplexing For Atm Ima Family
Manufacturer
Mindspeed Technologies
Datasheet

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Part Number
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Part Number:
M28529-12
Manufacturer:
MINDSPEE
Quantity:
1 238
Distinguishing Features
• Complete IMA solution in a single package
• Field tested software available
• Up to 32 IMA groups with 1-32 links/group
• Supports 50 ms (beyond the IMA standard requirements for 25 ms)
• Memory expandable to 2 M bytes via external bus
• UTOPIA level 2 interfaces
• Glueless serial and interleaved highway interfaces to Mindspeed
• Octet or Bit level cell delineation
• Variable link data rates (64K–8.192 Mb/s)
M28525/9 Data Sheet
Inverse Multiplexing for ATM (IMA) Family
The M2852x family of devices provides system designers with a complete integrated IMA solution for up to 32 ports.
All devices include a Transmission Convergence block to perform cell delineation, 512 K internal RAM to meet ATM
forum requirements for differential delay compensation and a dual mode (UTOPIA or Serial) PHY layer interface.
Source code for all required software functions is available from Mindspeed. The M28529 supports 32 IMA groups
with 1-32 links per group.
The TC block is capable of bit level cell delineation, which allows for direct connection DSL serial data streams
without a frame sync pulse. Individual ports can be operated in a 'pass thru' mode without the IMA overhead.
The M28529 provides direct connection to 32 serial/interleaved highway links or a PHY side UTOPIA bus. In
addition, an external memory bus allows the differential delay memory to access up to 2 Mbytes of external
RAM.The M28529 supports both version 1.0 and 1.1 of IMA standard AF-PHY-0086.001
28529-DSH-001-K
differential delay with 512K Internal memory
Framers
• 16 port, M28525
• 32 port, M28529
* N o t e : T h e M 2 8 5 2 5 o n l y s u p p o r t s 1 6 T C P o r t s
M 2 8 5 2 9
I n t e r n a l
5 1 2 K x 8
S R A M
IM A c l o c ks
0
D if f e r e n t ia l D e la y
i
m e m o r y in t e r f a c e
T x B lo c k a n d
R x B lo c k a n d
P a s s t h r o u g h
P a s s t h r o u g h
e x tm e m s e l p in
E n g i n e
I M A
E x t e rn a l M e m o r y
Mindspeed Proprietary and Confidential
Mindspeed Technologies
I n t e r f a c e
1
Functional Block Diagram
J T A G
B l o c k
I M A
I n t e r f a c e
M i c r o
®
C o u n te r s
T C
O n e S e c
T C B l o c k
T C S t a t u s
R e g i s te r s
p r o c e s s o r
p r o c e s s o r
p r o c e s s o r
p r o c e s s o r
C l o c ks
M i c r o
C e ll
C e ll
C e ll
C e ll
L in e in t e r f a c e 3 0
L in e in t e r f a c e 3 1
L in e in t e r f a c e
L in e in t e r f a c e
T C C o n tr o l
R e g i s te r s
0
1
September 2007

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