89ttm553 Integrated Device Technology, 89ttm553 Datasheet
89ttm553
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89ttm553 Summary of contents
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... The 89TTM553 stores all the flow-based parameters (and state infor- mation) that are made available to the 89TTM552 for flow-based processing. When the 89TTM553 is used with the 89TTM552, conges- tion and bandwidth management features are enabled at the flow level as well as at the aggregate-flow level. ...
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... IDT 89TTM553 Configurable forwarding based on classification index. Two ports for obtaining event-based statistics. Configurable on-chip diagnostic statistics. Bandwidth management rate guarantee and shaping mechanisms for each flow, each aggregate flow and each port queue. – Priority and weighted bandwidth distribution mechanisms across groups of flows and aggregate flows. ...
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... IDT 89TTM553 9TTM55x Functional Block Diagram 9TTM55x Functional Block Diagram 9TTM55x Functional Block Diagram 9TTM55x Functional Block Diagram Data Buffer Memory (DDR SDRAM) 89TTM552 Engine (DFC) SPI-4 Streaming DSR, Interface BRX or SIX-over-LVDS Forwarding and Thresholding Engine (AC) 89TTM553 Forwarding ...
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... Pin Description 89TTM553 Pin Description 89TTM553 Pin Description 89TTM553 Pin Description Note: Information in this section is subject to change. Contact your IDT FAE before making design decisions. In this data sheet, direction is indicated as follows: I for In, O for Out, B for Bi-directional, and P for power. ...
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... IDT 89TTM553 Signal Name BXT_WR_N 1.5V HSTL Class 1 BXT_DOUT[3:0] 1.5V HSTL Class 1 BXT_LLT_VREF 0.75V Signal Name FCT_CLK_CP, 1.5V HSTL Class 1 FCT_CLK_CN FCT_CLK_KP, 1.5V HSTL Class 1 FCT_CLK_KN FCT_ADDR[19:0] 1.5V HSTL Class 1 FCT_RD_N 1.5V HSTL Class 1 FCT_DIN[27:0] 1.5V HSTL Class 1 FCT_WR_N 1.5V HSTL Class 1 FCT_DOUT[27:0] 1.5V HSTL Class 1 FCT_VREF[1:0] 0.75 Signal Name FPT_CLK_CP, 1 ...
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... IDT 89TTM553 Signal Name FPT_DIN[35:0] 1.5V HSTL Class 1 FPT_WR_N 1.5V HSTL Class 1 FPT_BW_N[3:0] 1.5V HSTL Class 1 FPT_DOUT[35:0] 1.5V HSTL Class 1 FPT_VREF[1:0] 0.75V Signal Name GPT_CLK_CP, 1.5V HSTL Class 1 GPT_CLK_CN GPT_CLK_KP, 1.5V HSTL Class 1 GPT_CLK_KN GPT_ADDR[20:0] 1.5V HSTL Class 1 GPT_RD_N 1.5V HSTL Class 1 GPT_DIN[17:0] 1.5V HSTL Class 1 GPT_WR_N 1.5V HSTL Class 1 GPT_BW_N[1:0] 1 ...
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... IDT 89TTM553 Signal Name HT_CLK_CP, HT_CLK_CN 1.5V HSTL Class 1 HT_CLK_KP, 1.5V HSTL Class 1 HT_CLK_KN HT_ADDR[19:0] 1.5V HSTL Class 1 HT_RD_N 1.5V HSTL Class 1 HT_DIN[35:0] 1.5V HSTL Class 1 HT_WR_N 1.5V HSTL Class 1 HT_DOUT[35:0] 1.5V HSTL Class 1 HT_VREF[1:0] 0.75V Signal Name LLT_CLK_CP, 1.5V HSTL Class 1 LLT_CLK_CN LLT_CLK_KP, 1.5V HSTL Class 1 LLT_CLK_KN LLT_ADDR[19:0] 1.5V HSTL Class 1 LLT_RD_N 1 ...
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... Clock output to 89TTM552 I 175 MHz Cell time tic input from 89TTM552 O 175 MHz Cell time tic out to 89TTM552 — — HSTL reference. Nominally V Table 8 89TTM552/89TTM553 Interface I/O Type Dir. Freq ZBus address valid flag (active low) 66 MHz ZBus clock input ( MHz) ...
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... IDT 89TTM553 Signal Name IDDQ 3.3V, internal pulldown RESERVE_1 3.3V LVTTL drive SCAN_EN 3.3V RESERVE_0 3.3V, internal pullup TCK 3.3V TDI 3.3V, internal pullup TDO 3.3V LVTTL drive TMS 3.3V, internal pullup TRST_N 3.3V, internal pullup Signal Name PLL_2X_BPCLK 3.3V, internal pulldown PLL_BP_MODE 3.3V, internal pulldown PLL_MON 3.3V LVTTL, 12mA drive PLL_CFG_OVR 3 ...
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... IDT 89TTM553 Signal Name VDD33 — N/C — GND — 9TTM553 Electrical Specifications 9TTM553 Electrical Specifications 9TTM553 Electrical Specifications 9TTM553 Electrical Specifications Some data are TBD and will be published as they become available. The specifications are subject to change without notice bsolute Maximum Ratings ...
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... IDT 89TTM553 Symbol VDD 3.3V LVTTL supply 33 1 VRF 0.75V HSTL reference voltage HSTL Power Dissipation 1. This operating range applies to the following pins: BLL_VREF, BXT_LLT_VREF, FCT_VREF[1:0], FPT_VREF[1:0], GPT_VREF, HT_VREF[1:0], and FLQS_VREF. DC Characteristics DC Characteristics DC Characteristics DC Characteristics Unless otherwise stated, the following parameters are provided given the conditions outlined in Table 13. ...
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... IDT 89TTM553 Symbol I (3.3v pads w/ Input Leakage high current for 3.3V with Pull- IH33PU Pull Up) Up Inputs I (3.3v pads w/ Input Leakage low current for 3.3V with Pull- IL33PD Pull Down) Down Inputs I (3.3v pads w/ Input Leakage high current for 3.3V with Pull- IH33PD Pull Down) Down Inputs ...
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... Input Rise/Fall Time Output timing measurement reference level (V Output load For output timing 89TTM553 Thermal Considerations 89TTM553 Thermal Consideration 89TTM553 Thermal Consideration 89TTM553 Thermal Consideration This section describes the temperature and heat sink calculations for flip-chip BGA devices. Symbol Ø ...
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... Ø CA Ø versus Ø A CA. Ambient Temp. vs Ø 90.0 81.0 80.0 79.7 78.8 78.2 70.0 60.0 50.0 40.0 30.0 1.0 2.0 3.0 4.0 Ø CA Figure 3 89TTM553 Ambient Temperature Curve , without a heat sink, and is specified for various air-flow conditions. This is the intrinsic Ø that can be tolerated based A CA 77.7 77.2 76.9 76.6 5.0 6.0 7.0 8.0 o C/W March 3, 2005 ...
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... Reset Sequence 89TTM553 Reset Sequence A PLL reset sequence must be followed when resetting the 89TTM553 to ensure that clocks are stable when the chip comes out of reset. This section describes the reset sequence for the 89TTM553 device. The 89TTM553 uses data presented on the ZBus data and parity pins to determine the clock frequencies when the chip is in reset. The PLL_CFG_OVR pin controls this feature ...
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... PLL_CFG_OVR PLL_RST NOTE: - ZBUS_AD[ ] and ZBUS_PRTY[ ] are used to configure the chip operating frequency, and is listed on next page Pin List I/O Description Pin List I/O Description Pin List I/O Description Pin List I/O Description The 89TTM553 Pin List on page 17 uses the following I/O notations ...
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... IDT 89TTM553 9TTM553 Pin List 9TTM553 Pin List 9TTM553 Pin List 9TTM553 Pin List Pin Signal Type A2 GND P A3 VDD15 P A4 HT_CLK_CN I A5 HT_CLK_CP I A6 HT_DIN_19 I A7 HT_DIN_20 I A8 VDD15 P A9 GND P A10 HT_DIN_34 I A11 HT_DIN_35 I A12 HT_DOUT_14 O A13 ...
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... IDT 89TTM553 Pin Signal Type C20 GND P C21 VDD15 P C22 FCT_ADDR_01 O C23 FCT_ADDR_00 O C24 FCT_ADDR_18 O C25 FCT_ADDR_19 O C26 GND P C27 VDD15 P C28 FCT_DOUT_12 O C29 FCT_DOUT_13 O C30 FCT_DOUT_17 O C31 FCT_DOUT_16 O C32 FCT_DOUT_22 O C33 VDD15 P C34 VDD15 P D1 BLL_DIN_03 I D2 BLL_CLK_CP I D3 BLL_DIN_11 ...
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... IDT 89TTM553 Pin Signal Type F4 BLL_DIN_12 I F5 BLL_DIN_16 I F6 HT_DIN_00 I F7 HT_VREF_00 P F8 VDD15 P F9 GND P F10 HT_DIN_21 I F11 HT_DIN_22 I F12 HT_DOUT_00 O F13 HT_DOUT_01 O F14 VDD15 P F15 GND P F16 HT_DOUT_23 O F17 HT_DOUT_29 O F18 HT_ADDR_03 O F19 HT_ADDR_08 O F20 GND P F21 VDD15 P F22 ...
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... IDT 89TTM553 Pin Signal Type H22 HT_WR_N O H23 HT_RD_N O H24 FCT_DOUT_07 O H25 FCT_DOUT_06 O H26 GND P H27 GND P H28 VDD15 P H29 VDD15 P H30 VDD15 P H31 VDD15 P H32 VDD15 P H33 VDD15 P H34 VDD15 P J1 GND P J2 GND P J3 GND P J4 GND P J5 GND ...
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... IDT 89TTM553 Pin Signal Type M4 BLL_CLK_KP O M5 BLL_ADDR_21 O M6 BLL_ADDR_02 O M7 BLL_DOUT_00 O M8 BLL_ADDR_01 O M9 BLL_ADDR_00 O M26 FLQS_DOUT_06 O M27 FLQS_DOUT_13 O M28 FLQS_TIC_IN I M29 FLQS_DOUT_04 O M30 FLQS_DOUT_09 O M31 FLQS_CLKOUT O M32 FLQS_DOUT_11 O M33 FLQS_DOUT_16 O M34 FLQS_DOUT_17 O N1 BLL_ADDR_12 O N2 BLL_ADDR_14 O N3 BLL_ADDR_19 O N4 ...
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... IDT 89TTM553 Pin Signal Type T2 BLL_ADDR_11 O T3 BLL_ADDR_07 O T4 BLL_ADDR_06 O T5 BLL_ADDR_05 O T6 BLL_ADDR_04 O T7 BXT_WR_N O T8 BLL_ADDR_09 O T9 BLL_ADDR_08 O T14 GND P T15 VDD18 P T16 GND P T17 VDD18 P T18 GND P T19 VDD18 P T20 GND P T21 VDD18 P T26 FLQS_VREF P T27 FLQS_DIN_01 I T28 ...
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... IDT 89TTM553 Pin Signal Type W14 VDD18 P W15 GND P W16 VDD18 P W17 GND P W18 VDD18 P W19 GND P W20 VDD18 P W21 GND P W26 RESET_N I W27 PLL_SYS_REFCLK I W28 TRST_N I W29 PLL_BP_MODE I W30 PLL_MON O W31 PLL_CFG_OVR I W32 PLL_RST I W33 NC W34 PLL_VSSA I Y1 GND P Y2 ...
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... IDT 89TTM553 Pin Signal Type AB34 PLL_VDDA I AC1 BXT_DIN_03 I AC2 BXT_CLK_CN I AC3 LLT_DIN_10 I AC4 LLT_DIN_08 I AC5 LLT_DIN_07 I AC6 LLT_DIN_03 I AC7 BXT_DOUT_03 O AC8 BXT_DIN_01 I AC9 LLT_DIN_05 I AC26 ZBUS_AD_08 B AC27 ZBUS_AD_09 B AC28 ZBUS_AD_13 B AC29 ZBUS_AD_10 B AC30 ZBUS_AD_07 B AC31 ZBUS_AD_05 B AC32 ZBUS_AD_02 B AC33 ZBUS_CLK ...
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... IDT 89TTM553 Pin Signal Type AF32 GND P AF33 GND P AF34 GND P AG1 VDD15 P AG2 VDD15 P AG3 VDD15 P AG4 VDD15 P AG5 VDD15 P AG6 VDD15 P AG7 VDD15 P AG8 GND P AG9 GND P AG10 FPT_DIN_17 I AG11 FPT_DIN_18 I AG12 FPT_ADDR_15 O AG13 FPT_ADDR_16 O AG14 VDD15 P AG15 GND ...
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... IDT 89TTM553 Pin Signal Type AJ16 FPT_ADDR_03 O AJ17 FPT_DOUT_34 O AJ18 FPT_DOUT_24 O AJ19 FPT_DOUT_18 O AJ20 GND P AJ21 VDD15 P AJ22 GPT_RD_N O AJ23 GPT_ADDR_20 O AJ24 GPT_ADDR_07 O AJ25 GPT_ADDR_06 O AJ26 GND P AJ27 VDD15 P AJ28 GPT_DOUT_10 O AJ29 GPT_DOUT_00 O AJ30 GPT_DIN_16 I AJ31 GPT_DIN_12 I AJ32 GPT_DIN_08 I AJ33 GPT_DIN_06 ...
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... IDT 89TTM553 Pin Signal Type AL34 GPT_DIN_03 I AM1 VDD15 P AM2 VDD15 P AM3 FPT_DIN_32 I AM4 FPT_DIN_27 I AM5 FPT_DIN_28 I AM6 FPT_DIN_24 I AM7 FPT_DIN_23 I AM8 VDD15 P AM9 GND P AM10 FPT_DIN_09 I AM11 FPT_DIN_08 I AM12 FPT_ADDR_17 O AM13 FPT_ADDR_18 O AM14 VDD15 P AM15 GND P AM16 FPT_ADDR_06 O AM17 FPT_DOUT_31 ...
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... IDT 89TTM553 Pin Signal Type AP19 FPT_DOUT_11 O AP20 GND P AP21 VDD15 P AP22 FPT_DOUT_10 O AP23 FPT_DOUT_09 O AP24 GPT_ADDR_19 O AP25 GPT_ADDR_18 O AP26 GND P AP27 VDD15 P AP28 GPT_ADDR_05 O AP29 GPT_ADDR_04 O AP30 GPT_ADDR_02 O AP31 GPT_ADDR_03 O AP32 VDD15 P AP33 GND March 3, 2005 ...
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... Package 9TTM553 Package 9TTM553 Package 9TTM553 Package The package is an LSI Logic FPBGA-HP, having 960 pins, with 1 mm pitch ×34 pin array; and a 35 × enclosure. Figure 5 shows the package geometry. Figure 5 89TTM553 Package Diagram March 3, 2005 ...
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... IDT 89TTM553 Ordering Information Ordering Informatio Ordering Informatio Ordering Informatio Product Operating Device Family Voltage Family Valid Combinations Valid Combinations Valid Combinations Valid Combinations 89TTM553BL Revision History Revision History Revision History Revision History November 23, 2004: Initial publication by IDT. January 12, 2005: On page 14, deleted reference to LVDS in the Core PLL Frequency Setting heading. ...