cx28365 Mindspeed Technologies, cx28365 Datasheet

cx28365

Manufacturer Part Number

cx28365

Description

X12, X6, X4 T3/e3 Framer And Atm Cell Transmission Convergence Sublayer Processor

Manufacturer

Mindspeed Technologies

Datasheet

1.CX28365.pdf (228 pages)

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Preliminary Information

This document contains information on a new product. The parametric information, although not

fully characterized, is the result of testing initial devices.

CX28365/6/4

x12, x6, x4 T3/E3 Framer and ATM Cell

Transmission Convergence Sublayer

Processor

The CX2836x is a family of devices that provides up to twelve T3/E3 framers that

support DS3-M13, DS3-C-bit parity, E3-G.751, and E3-G.832 transmission formats

integrated with ATM physical layer processing functions. These functions are found

in the ATM Forum Cell-Based Transmission Convergence Sublayer Specification (af-phy-

0043.000), DS3 Physical Layer Interface S

UNI S

G.832 formatted signals. Access is provided to the FEAC and TDL channels.

flexibility to support the transmission and recovery of industry standard formats. It

provides a flexible opportunity bit generation method to source opportunity bits on

an individual framer.

and NNI ATM interfaces. A complete design for interfacing cells from a standard

UTOPIA Level 2 system interface to the physical line connections requires only the

addition of four triple Line Interface Units (LIUs) or a single twelve port LIU, and a

microprocessor for configuration and control.

The CX28365 is an x12 T3/E3 framer with transmission convergence. The CX28366

is an x6 T3/E3 framer with transmission convergence, and the CX28364 is a quad T3/

E3 framer with transmission convergence. Both the CX28366 and CX28364 perform

identically to the CX28365.

Data Sheet

The CX2836x provides framing recovery for M13, M23, C-bit parity, G.751, and

The CX2836x device allows for ease of configuration, while providing maximum

The CX2836x provides a high-density and low-cost solution for T3 and E3 UNI

pecification

(af-phy-0034.000).

Preliminary Information/Mindspeed Proprietary and Confidential

pecification

Mindspeed Technologies™

(af-phy-0054.000), and

Public

Distinguishing Features

Testing

Applications

Twelve, six, or four independent DS3/E3

framers in one package

Line coding supported:

Framing supported:

Inserts and extracts opportunity bits

Full FEAC and TDL channel support

Full performance monitoring support per

T1.231 standard

Glueless interfaces to the following

devices:

S-RAM-type processor interface

PLCP or direct framing selectable

per port

Power supplies and power consumption

UTOPIA Interface

Cell Delineator

JTAG boundary scan support

Digital Cross-Connect Systems

Optical Transport Equipment

Access Concentrators

ATM Switches

Concentrators

Routers

DS3: B3ZS, NRZ, AMI

E3: HDB3, NRZ, AMI

DS3: M13, M23, C-bit parity

E3: G.751, G.832

LIU Interfaces:

– Mindspeed's DS3/E3/STS-1 LIU

SAR interfaces: Bt8233/RS8234

Network processors: CX27440/

CX27460

HDLC controllers: CX23500

I/O 3.3 V, input 5 V tolerant, core 1.8 V

Low power operation (<190 mW per

port)

Level 2

8- and 16-bit modes

Multi-PHY capability

Redundant channel

Passes or rejects idle cells or selected

cells based on header register

configuration

Recovers cell alignment from HEC

Performs single-bit HEC error

correction and multiple-bit detection

Generates cell status bits, cell counts,

and error counts

Reads cell data from the UTOPIA FIFO

Inserts idle cells when no traffic is

available

ITU I.432-compliant

CX28333–1x, –3x, M28335

May 2002

500028C

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