k4x56163pe-lg Samsung Semiconductor, Inc., k4x56163pe-lg Datasheet
k4x56163pe-lg
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k4x56163pe-lg Summary of contents
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... K4X56163PE-L(F)G 16M x16 Mobile DDR SDRAM FEATURES • 1.8V power supply, 1.8V I/O power • Double-data-rate architecture; two data transfers per clock cycle • Bidirectional data strobe(DQS) • Four banks operation • Differential clock inputs(CK and CK) • MRS cycle with address key programs - CAS Latency ( Burst Length ( Burst Type (Sequential & ...
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... K4X56163PE-L(F)G Package Dimension and Pin Configuration < Bottom View ...
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... K4X56163PE-L(F)G Input/Output Function Description SYMBOL TYPE CK, CK Input Clock : CK and CK are differential clock inputs. All address and control input signals are sampled on the crossing of the positive edge of CK and negative edge of CK. Internal clock signals are derived from CK/CK. CKE Input Clock Enable : CKE HIGH activates, and CKE LOW deactivates internal clock signals, and device input buffers and output drivers ...
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... K4X56163PE-L(F)G Functional Description Simplified State Diagram EXTENDED MODE REGISTER SET MODE REGISTER SET POWER DOWN WRITEA WRITE WRITEA WRITEA POWER POWER APPLIED ON PARTIAL SELF REFRESH REFS EMRS REFSX MRS REFA IDLE CKEL CKEH ACT CKEH CKEL ROW BURST STOP ACTIVE WRITE ...
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... K4X56163PE-L(F)G Power Up Sequence for Mobile DDR SDRAM CKE ...
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... K4X56163PE-L(F)G Mode Register Definition Mode Register Set(MRS) The mode register is designed to support the various operating modes of DDR SDRAM. It includes CAS latency, addressing mode, burst length, test mode and vendor specific options to make DDR SDRAM useful for variety of applications. The default value of the mode register is not defined, therefore the mode register must be written in the power up sequence of DDR SDRAM ...
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... K4X56163PE-L(F)G Burst address ordering for burst length Burst Starting Address(A2, A1, A0) Length xx0 2 xx1 x00 x01 4 x10 x11 000 001 010 011 8 100 101 110 111 Mobile-DDR SDRAM Sequential Mode Interleave Mode ...
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... K4X56163PE-L(F)G Extended Mode Register Set(EMRS) The extended mode register is designed to support partial array self refresh or driver strength. EMRS cycle is not mandatory and the EMRS command needs to be issued only when either PASR used. The default state without EMRS command issued is +85 C, all 4 banks refreshed and the half size of driver strength ...
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... K4X56163PE-L(F)G Internal Temperature Compensated Self Refresh (TCSR) Note : 1. In order to save power consumption, Mobile DDR SDRAM includes the internal temperature sensor and control units to control the self refresh cycle automatically according to the two temperature range ; Max Max the EMRS for external TCSR is issued by the controller, this EMRS code for TCSR is ignored. ...
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... K4X56163PE-L(F)G Precharge The precharge command is used to precharge or close a bank that has been activated. The precharge command is issued when CS, RAS and WE are low and CAS is high at the rising edge of the clock. The precharge command can be used to precharge each bank respectively or all banks simultaneously. The bank select addresses(BA0, BA1) are used to define which bank is precharged when the command is initiated ...
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... K4X56163PE-L(F)G Row Active The Bank Activation command is issued by holding CAS and WE high with CS and RAS low at the rising edge of the clock(CK). The DDR SDRAM has four independent banks, so two Bank Select addresses(BA0, BA1) are required. The Bank Activation command must be applied before any Read or Write operation is executed. The delay from the Bank Activation command to the first read or write command must meet or exceed the minimum of RAS to CAS delay time(tRCD min) ...
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... K4X56163PE-L(F)G Essential Functionality for DDR SDRAM The essential functionality that is required for the DDR SDRAM device is described in this chapter Burst Read Operation Burst Read operation in DDR SDRAM is in the same manner as the SDRAM such that the Burst read command is issued by assert- ing CS and CAS low while holding RAS and WE high at the rising edge of the clock(CK) after tRCD from the bank activation ...
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... K4X56163PE-L(F)G Burst Write Operation The Burst Write command is issued by having CS, CAS, and WE low while holding RAS high at the rising edge of the clock(CK). The address inputs determine the starting column address. There is no write latency relative to DQS required for burst write cycle. The first data of a burst write cycle must be applied on the DQ pins tDS(Data-in setup time) prior to data strobe edge enabled after tDQSS from the rising edge of the clock(CK) that the write command is issued ...
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... K4X56163PE-L(F)G Read Interrupted by a Read A Burst Read can be interrupted before completion of the burst by new Read command of any bank. When the previous burst is interrupted, the remaining addresses are overridden by the new address with the full burst length. The data from the first Read com- mand continues to appear on the outputs until the CAS latency from the interrupting Read command is satisfied ...
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... K4X56163PE-L(F)G Read Interrupted by a Precharge A Burst Read operation can be interrupted by precharge of the same bank. The minimum 1 clock is required for the read to precharge intervals. A precharge command to output disable latency is equivalent to the CAS latency. < Burst Length=8, CAS Latency=3 > CK, CK 1tCK Precharge Command ...
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... K4X56163PE-L(F)G Write Interrupted by a Write A Burst Write can be interrupted before completion of the burst by a new Write command, with the only restriction that the interval that separates the commands must be at least one clock cycle. When the previous burst is interrupted, the remaining addresses are overridden by the new address and data will be written into the device until the programmed burst length is satisfied. < ...
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... K4X56163PE-L(F)G Write Interrupted by a Precharge & burst write operation can be interrupted before completion of the burst by a precharge of the same bank. Random column access is allowed. A write recovery time(tWR) is required from the last data to precharge command. When precharge command is asserted, any residual data from the burst write cycle must be masked by DM. ...
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... K4X56163PE-L(F)G 3. For a Write with autoprecharge command, a new Bank Activate command may be issued to the same bank after tWR+tRP where tWR+tRP starts on the falling DQS edge that strobed in the last valid data and ends on the rising clock edge that strobes in the Bank Activate command. During write with autoprecharge, the initiation of the internal precharge occurs at the same time as the earliest possible external Precharge command without interrupting the Write burst as described in 1 above ...
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... K4X56163PE-L(F)G DM masking The DDR SDRAM has a data mask function that can be used in conjunction with data write cycle, not read cycle. When the data mask is activated (DM high) during write operation, DDR SDRAM does not accept the corresponding data.(DM to data-mask latency is zero). ...
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... K4X56163PE-L(F)G Read With Auto Precharge If a read with auto-precharge command is issued, the DDR SDRAM automatically enters the precharge operation BL/2 clock later from a read with auto-precharge command when tRAS(min) is satisfied. If not, the start point of precharge operation will be delayed until tRAS(min) is satisfied. Once the precharge operation has started, the bank cannot be reactivated and the new command can not be asserted until the precharge time(tRP) has been satisfied. < ...
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... K4X56163PE-L(F)G Write with Auto Precharge If A10 is high when write command is issued , the write with auto-precharge function is performed. Any new command to the same bank should not be issued until the internal precharge is completed. The internal precharge begins after keeping tWR(min). < Burst Length=4 > ...
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... K4X56163PE-L(F)G Auto Refresh & Self Refresh Auto Refresh An auto refresh command is issued by having CS, RAS and CAS held low with CKE and WE high at the rising edge of the clock(CK). All banks must be precharged and idle for tRP(min) before the auto refresh command is applied. No control of the external address pins is required once this cycle has started because of the internal address counter ...
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... K4X56163PE-L(F)G Power down The device enters power down mode when CKE Low,and it exits when CKE High. Once the power down mode is initiated, all of the receiver circuits except CK and CKE are gated off to reduce power consumption. The both bank should be in idle state prior to enter- ing the precharge power down mode and CKE should be set high at least 1 tCK+tIS prior to Row active command ...
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... K4X56163PE-L(F)G Command Truth Table (V=Valid, X=Don t Care, H=Logic High, L=Logic Low) COMMAND Register Mode Register Set Auto Refresh Entry Refresh Self Refresh Exit Bank Active & Row Addr. Read & Auto Precharge Disable Column Address Auto Precharge Enable Write & Auto Precharge Disable ...
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... K4X56163PE-L(F)G Functional Truth Table Current State CS RAS CAS PRECHARGE STANDBY ACTIVE STANDBY READ ...
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... K4X56163PE-L(F)G Functional truth table Current State CS RAS CAS WRITE READ with AUTO PRECHARGE (READA WRITE with AUTO RECHARGE ...
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... K4X56163PE-L(F)G Functional truth table Current State CS RAS CAS PRECHARGING L H (DURING tRP ROW L H ACTIVATING L H (FROM ROW L L ACTIVE TO tRCD WRITE L H RECOVERING L H (DURING tWR tCDLR ...
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... K4X56163PE-L(F)G Functional truth table Current State CS RAS CAS RE FRESHING MODE REGISTER SETTING Address Command L X Burst Stop X BA, CA, A10 READ/WRITE H BA, RA Active L BA, A10 ...
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... K4X56163PE-L(F)G Functional truth table CKE CKE Current State CS n-1 n SELF REFRESHING POWER DOWN ALL BANKS IDLE ANY STATE ...
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... Table 10. Absolute maximum ratings K4X56163PE-L(F)G Absolute maximum ratings Parameter Voltage on any pin relative Voltage on V supply relative Voltage on V supply relative to V DDQ Storage temperature Power dissipation Short circuit current Note : Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. ...
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... K4X56163PE-L(F)G DC CHARACTERISTICS Recommended operating conditions (Voltage referenced to V Parameter Symbol Operating Current I CC0 (One Bank Active CC2 Precharge Standby Current in power-down mode I PS CC2 I N CC2 Precharge Standby Current in non power-down mode I NS CC2 I P CC3 Active Standby Current in power-down mode ...
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... K4X56163PE-L(F)G 3. Definitions for IDD: LOW is defined DDQ ; IN HIGH is defined DDQ ; IN STABLE is defined as inputs stable at a HIGH or LOW level; SWITCHING is defined as: - address and command: inputs changing between HIGH and LOW once per two clock cycles - data bus inputs: DQ changing between HIGH and LOW once per clock cycle; DM and DQS are STABLE. ...
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... K4X56163PE-L(F)G AC Timming Parameters & Specifications Parameter Clock cycle time Row cycle time Row active time RAS to CAS delay Row precharge time Row active to Row active delay Write recovery time Last data in to Active delay Last data in to Read command Col. address to Col. address delay ...
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... K4X56163PE-L(F)G 1. Input Setup/Hold Slew Rate Derating Input Setup/Hold Slew Rate (V/ns) 1.0 0.8 0.6 This derating table is used to increase Minimum 3CLK of tDAL(= tWR + tRP) is required because it need minimum 2CLK for tWR and minimum 1CLK for tRP. 3. tSAC(min) value is measured at the high Vdd(1.95V) and cold temperature(-25 C). ...
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... K4X56163PE-L(F)G AC Operating Test Conditions Parameter AC input levels (Vih/Vil) Input timing measurement reference level Input signal minimum slew rate Output timing measurement reference level Output load condition 1.8V 13.9K V Output V 30pF 10.6K (Fig Output Load Circuit Input/Output Capacitance (V DD Parameter Input capacitance (A0 ~ A12, BA0 ~ BA1, CKE, CS, RAS,CAS, WE) Input capacitance( CK Data & ...
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... K4X56163PE-L(F)G Basic Timing (Setup, Hold and Access Time @BL=4, CL= CKE ...
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... K4X56163PE-L(F)G Multi Bank Interleaving READ (@BL=4, CL= CKE ...
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... K4X56163PE-L(F)G Multi Bank Interleaving WRITE (@BL= CKE ...
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... K4X56163PE-L(F)G Read with Auto Precharge (@BL= CKE ...
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... K4X56163PE-L(F)G Write with Auto Precharge (@BL= CKE ...
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... K4X56163PE-L(F)G Write followed by Precharge (@BL= CKE ...
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... K4X56163PE-L(F)G Write Interrupted by Precharge & DM (@BL= CKE ...
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... K4X56163PE-L(F)G Write Interrupted by a Read (@BL=8, CL= CKE ...
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... K4X56163PE-L(F)G Read Interrupted by Precharge (@BL= CKE ...
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... K4X56163PE-L(F)G Read Interrupted by a Write & Burst Stop (@BL=8, CL= CKE ...
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... K4X56163PE-L(F)G Read Interrupted by a Read (@BL=8, CL= CKE ...
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... K4X56163PE-L(F)G DM Function (@BL=8) only for write CKE ...
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... K4X56163PE-L(F)G Mode Register Set CKE ...