FST16210_05 FAIRCHILD [Fairchild Semiconductor], FST16210_05 Datasheet
FST16210_05
Manufacturer Part Number
FST16210_05
Description
20-Bit Bus Switch
Manufacturer
FAIRCHILD [Fairchild Semiconductor]
Datasheet
1.FST16210_05.pdf
(4 pages)
© 2005 Fairchild Semiconductor Corporation
FST16210MTD
FST16210
20-Bit Bus Switch
General Description
The Fairchild Switch FST16210 provides 20-Bits of high-
speed CMOS TTL-compatible bus switching. The low on
resistance of the switch allows inputs to be connected to
outputs without adding propagation delay or generating
additional ground bounce noise.
The device is organized as a 10-bit or 20-Bit bus switch.
When OE
nected to Port 1B. When OE
to Port 2B.
Ordering Code:
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Connection Diagram
Pin Descriptions
Order Number
1
is LOW, the switch is ON and Port 1A is con-
Pin Name
OE
1A, 2A
1B, 2B
1
, OE
Package Number
2
MTD48
2
is LOW, Port 2A is connected
Bus Switch Enables
Description
Bus A
Bus B
48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
DS500193
Features
Logic Diagram
Truth Table
4
Minimal propagation delay through the switch.
Low l
Zero bounce in flow-through mode.
Control inputs compatible with TTL level.
:
OE
switch connection between two ports.
H
H
L
L
Package Description
CC
1
Inputs
.
OE
H
H
L
L
2
1A
1A
1A, 1B
November 1998
Revised June 2005
Z
Z
Inputs/Outputs
1B
1B
www.fairchildsemi.com
2A
2A
2A, 2B
Z
Z
2B
2B
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FST16210_05 Summary of contents
Page 1
FST16210 20-Bit Bus Switch General Description The Fairchild Switch FST16210 provides 20-Bits of high- speed CMOS TTL-compatible bus switching. The low on resistance of the switch allows inputs to be connected to outputs without adding propagation delay or generating additional ...
Page 2
Absolute Maximum Ratings Supply Voltage ( Switch Voltage ( Input Voltage (V ) (Note Input Diode Current ( Output (I ) Sink Current OUT ...
Page 3
AC Electrical Characteristics Symbol Parameter t ,t Propagation Delay Bus to Bus PHL PLH (Note Output Enable Time PZH PZL Output Disable Time PHZ PLZ Note 6: This parameter is guaranteed by design ...
Page 4
Physical Dimensions inches (millimeters) unless otherwise noted 48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide Technology Description The Fairchild Switch family derives from and embodies Fairchild’s proven switch technology used for several years in its 74LVX3L384(FST3384) bus ...