M25P05-AVDW6G NUMONYX [Numonyx B.V], M25P05-AVDW6G Datasheet
M25P05-AVDW6G
Related parts for M25P05-AVDW6G
M25P05-AVDW6G Summary of contents
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... RES instruction, one-byte, signature (05h), for backward compatibility More than 100,000 erase/program cycles per sector More than 20 years data retention ECOPACK® packages available April 2008 SO8 (MN) 150 mil width VFQFPN8 (MP) (MLP8) TSSOP8 (DW) UFDFPN8 (MB Rev 11 M25P05-A 1/52 www.numonyx.com 1 ...
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... Polling during a write, program or erase cycle . . . . . . . . . . . . . . . . . . . . . 12 4.4 Active power, standby power and deep power-down modes . . . . . . . . . . 12 4.5 Status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 4.5.1 4.5.2 4.5.3 4.5.4 4.6 Protection modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 4.7 Hold condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 5 Memory organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 6 Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 6.1 Write enable (WREN 6.2 Write disable (WRDI 6.3 Read identification (RDID 2/52 WIP bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 WEL bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 BP1, BP0 bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 SRWD bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 M25P05-A ...
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... M25P05-A 6.4 Read status register (RDSR 6.4.1 6.4.2 6.4.3 6.4.4 6.5 Write status register (WRSR 6.6 Read data bytes (READ 6.7 Read data bytes at higher speed (FAST_READ 6.8 Page program (PP 6.9 Sector erase (SE 6.10 Bulk erase (BE 6.11 Deep power-down (DP 6.12 Release from deep power-down and read electronic signature (RES Power-up and power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 8 Initial delivery state ...
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... Table 20. TSSOP8 – 8 lead thin shrink small outline, package mechanical data Table 21. UFDFPN8 (MLP8) – 8 lead ultra thin fine pitch dual flat package no lead package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 Table 22. Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 Table 23. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 4/52 M25P05-A ...
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... M25P05-A List of figures Figure 1. Logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Figure 2. SO, VFQFPN and TSSOP connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Figure 3. Bus master and memory devices on the SPI bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Figure 4. SPI modes supported . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Figure 5. Hold condition activation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Figure 6. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Figure 7. Write enable (WREN) instruction sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Figure 8. Write disable (WRDI) instruction sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Figure 9 ...
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... Description 1 Description The M25P05 512-Kbit (64 Kbits ×8) serial flash memory, with advanced write protection mechanisms, accessed by a high speed SPI-compatible bus. The memory can be programmed 1 to 256 bytes at a time, using the page program instruction. The memory is organized as 2 sectors, each containing 128 pages. Each page is 256 bytes wide ...
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... Figure 2. SO, VFQFPN and TSSOP connections 1. There is an exposed central pad on the underside of the VFQFPN package. This is pulled, internally and must not be allowed to be connected to any other voltage or signal line on the PCB See Package mechanical M25P05 ...
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... To start the Hold condition, the device must be selected, with Chip Select (S) driven Low. 2.6 Write Protect (W) The main purpose of this input signal is to freeze the size of the area of memory that is protected against program or erase instructions (as specified by the values in the BP1 and BP0 bits of the status register). 8/52 M25P05-A ...
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... M25P05-A 2.7 V supply voltage the supply voltage. CC 2.8 V ground the reference for the V SS supply voltage. CC Signal descriptions 9/52 ...
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... Serial Data output (Q) line at a time, the other devices are high impedance. Resistors R (represented in that the M25P05-A is not selected if the bus master leaves the S line in the high impedance state. As the bus master may enter a state where all inputs/outputs are in high impedance at ...
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... M25P05-A Example pF, that is R*C p master never leaves the SPI bus in the high impedance state for a time period shorter than 5 µs. Figure 4. SPI modes supported CPOL CPHA µs <=> the application must ensure that the bus p MSB ...
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... Table 14: Instruction times). ). Section 6.11: Deep power-down ). PP Section 6.8: Page , The device CC2 (DP)). This can be used as an extra M25P05-A ). The BE . CC1 ...
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... M25P05-A 4.5 Status register The status register contains a number of status and control bits, as shown in can be read or set (as appropriate) by specific instructions. 4.5.1 WIP bit The write in progress (WIP) bit indicates whether the memory is busy with a write status register, program or erase cycle. 4.5.2 WEL bit The write enable latch (WEL) bit indicates the status of the internal write enable latch. ...
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... The environments where non-volatile memory devices are used can be very noisy. No SPI device can operate correctly in the presence of excessive noise. To help combat this, the M25P05-A features the following data protection mechanisms: Power on reset and an internal timer (t changes while the power supply is outside the operating specification ...
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... M25P05-A 4.7 Hold condition The Hold (HOLD) signal is used to pause any serial communications with the device without resetting the clocking sequence. However, taking this signal Low does not terminate any write status register, program or erase cycle that is currently in progress. To enter the hold condition, the device must be selected, with Chip Select (S) Low. ...
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... Each page can be individually programmed (bits are programmed from 1 to 0). The device is sector or bulk erasable (bits are erased from but not page erasable. Table 3. Memory organization Sector 1 0 16/52 Address range 08000h 00000h M25P05-A 0FFFFh 07FFFh ...
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... M25P05-A Figure 6. Block diagram HOLD W Control logic Address register and counter High voltage generator I/O shift register 256 byte data buffer 08000h 00000h 256 bytes (page size) X decoder Memory organization Status register 0FFFFh Size of the read-only memory area 000FFh AI05759 ...
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... Chip Select (S) being driven Low is an exact multiple of eight. All attempts to access the memory array during a write status register cycle, program cycle or erase cycle are ignored, and the internal write status register cycle, program cycle or erase cycle continues unaffected. 18/52 Table 4. M25P05-A ...
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... M25P05-A Table 4. Instruction set Instruction WREN Write enable WRDI Write disable (1) RDID Read identification RDSR Read status register WRSR Write status register READ Read data bytes Read data bytes at higher FAST_READ speed PP Page program SE Sector erase BE Bulk erase DP Deep power-down Release from deep power- ...
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... Write status register (WRSR) instruction completion Page program (PP) instruction completion Sector erase (SE) instruction completion Bulk erase (BE) instruction completion. Figure 8. Write disable (WRDI) instruction sequence 20/52 (Figure 8) resets the write enable latch (WEL) bit Instruction D High Impedance AI03750D M25P05-A ...
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... M25P05-A 6.3 Read identification (RDID) The read identification (RDID) instruction is available in products with process technology code X and Y. The read identification (RDID) instruction allows the 8-bit manufacturer identification to be read, followed by two bytes of device identification. The manufacturer identification is assigned by JEDEC, and has the value 20h for Numonyx. The device identification is assigned by the device manufacturer, and indicates the memory type in the first byte (20h), and the memory capacity of the device in the second byte (10h) ...
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... BP1, BP0) become read-only bits and the write status register (WRSR) instruction is no longer accepted for execution. 22/ Figure 10. BP1 BP0 WEL Block protect bits Write enable latch bit Write in progress bit Table 2) becomes protected M25P05-A b0 WIP ...
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... M25P05-A Figure 10. Read status register (RDSR) instruction sequence and data-out sequence High Impedance Q 6.5 Write status register (WRSR) The write status register (WRSR) instruction allows new values to be written to the status register. Before it can be accepted, a write enable (WREN) instruction must previously have been executed ...
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... BP0) bits of the status register, can be used. Figure 11. Write status register (WRSR) instruction sequence 24/ Instruction High Impedance MSB M25P05-A Status register AI02282D ...
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... M25P05-A Table 7. Protection modes W SRWD signal bit Hardware defined by the values in the block protect (BP1, BP0) bits of the status register, as shown in Write protection of the status Mode register Status register is writable (if the WREN instruction has set the WEL Software bit) ...
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... High Impedance Q 1. Address bits A23 to A16 must be set to 00h. 26/52 Figure 12 Instruction 24-bit address MSB Data out MSB M25P05-A Data out 2 7 AI03748D ...
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... M25P05-A 6.7 Read data bytes at higher speed (FAST_READ) The device is first selected by driving Chip Select (S) Low. The instruction code for the read data bytes at higher speed (FAST_READ) instruction is followed by a 3-byte address (A23- A0) and a dummy byte, each bit being latched-in during the rising edge of Serial Clock (C). ...
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... At some unspecified time before the cycle is completed, the write enable latch (WEL) bit is reset. A page program (PP) instruction applied to a page which is protected by the block protect (BP1, BP0) bits (see 28/52 Figure 14. Table 3. and Table 2.) is not executed. M25P05-A Table 14: Instruction ...
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... M25P05-A Figure 14. Page program (PP) instruction sequence MSB 1. Address bits A23 to A16 must be set to 00h Instruction 24-bit address MSB Data byte 2 Data byte ...
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... Address bits A23 to A16 must be set to 00h. 30/ valid address for the sector erase (SE) instruction. Chip Select (S) Figure 15. Table 3 and Table 2) is not executed Instruction 23 22 MSB 24-bit address AI03751D M25P05 ...
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... M25P05-A 6.10 Bulk erase (BE) The bulk erase (BE) instruction sets all bits to ‘1’ (FFh). Before it can be accepted, a write enable (WREN) instruction must previously have been executed. After the write enable (WREN) instruction has been decoded, the device sets the write enable latch (WEL). ...
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... Any deep power-down (DP) instruction, while an erase, program or write cycle is in progress, is rejected without having any effects on the cycle that is in progress. Figure 17. Deep power-down (DP) instruction sequence 32/52 Figure 17 Instruction M25P05 specified CC1 CC2 before the supply current is reduced Standby mode Deep power-down mode AI03753D ...
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... The instruction can also be used to read, on Serial Data output (Q), the 8-bit electronic signature, whose value for the M25P05-A is 05h. Except while an erase, program or write status register cycle is in progress, the release from deep power-down and read electronic signature (RES) instruction always provides access to the 8-bit electronic signature of the device, and can be applied even if the deep power- down mode has not been entered ...
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... Figure 18. Release from deep power-down and read electronic signature (RES) instruction sequence and data-out sequence Instruction D High Impedance Q 1. The value of the 8-bit electronic signature, for the M25P05-A, is 05h. Figure 19. Release from deep power-down (RES) instruction sequence Instruction D High Impedance Q 34/ ...
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... M25P05-A 7 Power-up and power-down At power-up and power-down, the device must not be selected (that is Chip Select (S) must follow the voltage applied (min) at power-up, and then for a further delay power-down SS A safe configuration is provided in To avoid data corruption and inadvertent write operations during power-up, a power on reset (POR) circuit is included ...
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... The device is delivered with the memory array erased: all bits are set to ‘1’ (each byte contains FFh). The status register contains 00h (all status register bits are 0). 36/52 Program, erase and write commands are rejected by the device Chip selection not allowed tVSL tPUW threshold WI Parameter M25P05-A Read access allowed Device fully accessible time Min Max ...
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... M25P05-A 9 Maximum ratings Stressing the device above the rating listed in cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those indicated in the operating sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability ...
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... OUT C Input capacitance (other pins Sampled only, not 100% tested 38/52 Parameter (1) Parameter Input levels 0.8V CC 0.2V CC (1) Parameter Test condition OUT °C and a frequency of 25 MHz. A M25P05-A Min Max (1) 2.3 3.6 – Min Max 30 5 0. 0. ...
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... M25P05-A Table 13. DC characteristics Symbol I Input leakage current LI I Output leakage current LO I Standby current CC1 I Deep power-down current CC2 I Operating current (READ) CC3 I Operating current (PP) CC4 I Operating current (WRSR) CC5 I Operating current (SE) CC6 I Operating current (BE) CC7 V Input low voltage IL V Input high voltage ...
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... CL 2. Value guaranteed by characterization, not 100% tested in production. 3. Expressed as a slew-rate. 4. Only applicable as a constraint for a WRSR instruction when SRWD is set to ‘1’. 40/52 Test conditions specified in Table 10 Parameter (3) (peak to peak) (3) (peak to peak M25P05-A and Table 11. Min Typ Max Unit D.C. 25 MHz D.C. 20 MHz ...
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... M25P05-A Table 16. AC characteristics (40 MHz operation) 40 MHz available for products marked since week 20 of 2004, only Symbol Alt. Clock frequency for the following instructions FAST_READ, PP, SE, BE, DP, RES, WREN, WRDI RDSR, WRSR f Clock frequency for read instructions R ( Clock high time ...
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... FAST_READ, (5) (peak to peak) (5) (peak to peak (1)(2) and Table 11. Min Typ Max D. 0.1 0 100 100 30 30 M25P05-A Unit MHz MHz ns ns V/ns V/ µs µs µs ...
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... M25P05-A Figure 22. Serial input timing S tCHSL C tDVCH D High Impedance Q Figure 23. Write protect setup and hold timing during WRSR when SRWD =1 W tWHSL High Impedance Q tSLCH tCHDX tCLCH MSB IN DC and AC parameters tSHSL tCHSH tSHCH tCHCL LSB IN AI01447C tSHWL AI07439 43/52 ...
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... DC and AC parameters Figure 24. Hold timing HOLD Figure 25. Output timing S C tCLQV tCLQX tCLQX Q ADDR D .LSB IN 44/52 tHLCH tCHHL tCHHH tHLQZ tCH tCLQV tQLQH tQHQL M25P05-A tHHCH tHHQX AI02032 tCL tSHQZ LSB OUT AI01449e ...
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... M25P05-A 11 Package mechanical In order to meet environmental requirements, Numonyx offers these devices in ECOPACK® packages. These packages have a lead-free second level interconnect. The category of second level interconnect is marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. Figure 26. SO8N – ...
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... ddd C inches Typ Min 0.033 0.031 0.000 0.026 0.008 0.016 0.014 0.236 0.226 0.134 0.126 0.197 0.187 0.157 0.150 0.050 – 0.004 0.000 0.024 0.020 M25P05-A 70-ME Max 0.039 0.002 0.019 0.142 0.169 – 0.029 12° 0.006 0.004 0.002 ...
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... M25P05-A Figure 28. TSSOP8 – 8 lead thin shrink small outline, package outline Drawing is not to scale. Table 20. TSSOP8 – 8 lead thin shrink small outline, package mechanical data Symbol α millimeters Typ ...
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... A1 millimeters Typ Min Max 0.55 0.45 0.60 0.02 0.00 0.05 0.25 0.20 0.30 2.00 1.90 2.10 1.60 1.50 1.70 0.08 3.00 2.90 3.10 0.20 0.10 0.30 0.50 – – 0.45 0.40 0.50 0.15 0.30 M25P05 UFDFPN-01 inches Typ Min Max 0.022 0.018 0.024 0.001 0.000 0.002 0.010 0.008 0.012 0.079 0.075 0.083 0.063 0.059 0.067 0.003 0.118 0.114 0.122 0.008 0.004 0.012 0.020 – – ...
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... The TSSOP8 package is available in products with process technology code X and Y (details of how to find the process on the device marking are given in application note AN1995). Note: For a list of available options (speed, package, etc.) or for further information on any aspect of this device, please contact your nearest Numonyx sales office. Ordering information M25P05 49/52 ...
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... Figure 26. and Table Page programming, times. Section 11: Package mechanical). updated and Section Table 9.: Absolute maximum descriptions added. Figure 3: Bus updated, note 2 removed Section 7: Power-up and power- max modified in Table 9: Absolute maximum IO Section 11: M25P05-A (max), CC3 and LEAD paragraph 18). Page ...
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... M25P05-A Table 23. Document revision history (continued) Date Revision 07-Aug-2007 10-Oct-2007 10-Dec-2007 18-Apr-2008 Removed ‘low voltage’ from the title. Small text changes. Changed note below Table 12: Changed the minimum value for V UFDFPN8 package (MLP8) added. 8 Frequency test condition modified for I t (typ), t ...
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... Copies of documents which have an order number and are referenced in this document, or other Numonyx literature may be obtained by Numonyx StrataFlash is a trademark or registered trademark of Numonyx or its subsidiaries in the United States and other countries. *Other names and brands may be claimed as the property of others. 52/52 Please Read Carefully: applications. visiting Numonyx's website at http://www.numonyx.com. Copyright © 11/5/7, Numonyx, B.V., All Rights Reserved. M25P05-A ...