74HC/HCT107 Philips Semiconductors (Acquired by NXP), 74HC/HCT107 Datasheet
74HC/HCT107
Related parts for 74HC/HCT107
74HC/HCT107 Summary of contents
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... DATA SHEET For a complete data sheet, please also download: The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications The IC06 74HC/HCT/HCU/HCMOS Logic Package Information The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines 74HC/HCT107 Dual JK flip-flop with reset; negative-edge trigger Product specification File under Integrated Circuits, IC06 ...
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... Dual JK flip-flop with reset; negative-edge trigger FEATURES Output capability: standard I category: flip-flops CC GENERAL DESCRIPTION The 74HC/HCT107 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. QUICK REFERENCE DATA GND = ...
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... NAME AND FUNCTION synchronous inputs; flip-flops 1 and 2 complement flip-flop outputs true flip-flop outputs ground (0 V) clock input (HIGH-to-LOW, edge-triggered) asynchronous reset inputs (active LOW) positive supply voltage Fig.2 Logic symbol. 3 Product specification 74HC/HCT107 Fig.3 IEC logic symbol. ...
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... HIGH-to-LOW CP transition X = don’t care = HIGH-to-LOW CP transition December 1990 Fig.5 Logic diagram (one flip-flop). INPUTS nR nCP Product specification 74HC/HCT107 OUTPUTS ...
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... Product specification 74HC/HCT107 . TEST CONDITIONS UNIT WAVEFORMS 125 (V) 240 2 4.5 Fig.6 41 6.0 240 2 4.5 Fig.6 41 6.0 235 2 4.5 Fig.7 40 6.0 110 2 4.5 Fig ...
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... Product specification 74HC/HCT107 . TEST CONDITIONS UNIT 125 WAVEFORMS ( 4.5 Fig 4.5 Fig 4.5 Fig 4.5 Fig 4.5 Fig 4.5 Fig.7 ...
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... HCT 1 GND Fig.7 Waveforms showing the reset (nR) input to output (nQ, nQ) propagation delays, the reset pulse width and the nR to nCP removal time. PACKAGE OUTLINES See “74HC/HCT/HCU/HCMOS Logic Package Outlines” December 1990 . 7 Product specification 74HC/HCT107 ...