74HC/HCT161 Philips Semiconductors (Acquired by NXP), 74HC/HCT161 Datasheet
74HC/HCT161
Related parts for 74HC/HCT161
74HC/HCT161 Summary of contents
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... For a complete data sheet, please also download: The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications The IC06 74HC/HCT/HCU/HCMOS Logic Package Information The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines 74HC/HCT161 Presettable synchronous 4-bit binary counter; asynchronous reset Product specification File under Integrated Circuits, IC06 ...
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... Output capability: standard I category: MSI CC GENERAL DESCRIPTION The 74HC/HCT161 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. The 74HC/HCT161 are synchronous presettable binary counters which feature an internal look-ahead carry and can be used for high-speed counting ...
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... V) parallel enable input (active LOW) count enable carry input flip-flop outputs terminal count output positive supply voltage Fig.2 Logic symbol. 3 Product specification 74HC/HCT161 Fig.3 IEC logic symbol. ...
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... LOW-to-HIGH CP transition X = don’t care = LOW-to-HIGH CP transition December 1990 Fig.4 Functional diagram. INPUTS MR CP CEP CET Product specification 74HC/HCT161 OUTPUTS ( ( count ( ...
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... Philips Semiconductors Presettable synchronous 4-bit binary counter; asynchronous reset Fig.6 Typical timing sequence: reset outputs to zero; preset to binary twelve; count to thirteen, fourteen, fifteen, zero, one and two; inhibit. December 1990 Fig.5 State diagram. 5 Product specification 74HC/HCT161 ...
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... Philips Semiconductors Presettable synchronous 4-bit binary counter; asynchronous reset December 1990 Fig.7 Logic diagram. 6 Product specification 74HC/HCT161 ...
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... Product specification 74HC/HCT161 . TEST CONDITIONS UNIT 125 WAVEFORMS (V) min. max. 285 ns 2.0 Fig.8 57 4.5 48 6.0 325 ns 2.0 Fig.8 65 4.5 55 6.0 315 ns 2.0 Fig.9 63 4.5 54 6.0 330 ns 2 ...
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... Product specification 74HC/HCT161 TEST CONDITIONS UNIT 125 WAVEFORMS (V) min. max. 255 ns 2.0 Fig.12 51 4 2.0 Figs 11 and 12 0 4.5 0 6.0 3.0 MHz 2.0 Fig ...
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... Product specification 74HC/HCT161 . TEST CONDITIONS UNIT WAVEFORMS 125 (V) min. max 4.5 Fig 4.5 Fig 4.5 Fig 4.5 Fig 4.5 Fig. ...
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... C) amb 74HCT min. typ. max. min. max Product specification 74HC/HCT161 TEST CONDITIONS UNIT WAVEFORMS 125 (V) min. max 4.5 Fig. 4.5 Fig. 4.5 Fig. 4.5 Figs 11 and 12 15 MHz 4 ...
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... 50 GND HCT 1 GND Fig.10 Waveforms showing the input (CET) to output (TC) propagation delays and output transition times. December 1990 , TC) propagation delays, the clock pulse width, the n 11 Product specification 74HC/HCT161 , TC) propagation n ...
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... 50 GND HCT 1 GND Fig.12 Waveforms showing the CEP and CET set-up and hold times. PACKAGE OUTLINES See “74HC/HCT/HCU/HCMOS Logic Package Outlines” December 1990 ) and parallel enable input PE Product specification 74HC/HCT161 ...