74HC/HCT165 Philips Semiconductors (Acquired by NXP), 74HC/HCT165 Datasheet
74HC/HCT165
Related parts for 74HC/HCT165
74HC/HCT165 Summary of contents
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... DATA SHEET For a complete data sheet, please also download: The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications The IC06 74HC/HCT/HCU/HCMOS Logic Package Information The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines 74HC/HCT165 8-bit parallel-in/serial-out shift register Product specification File under Integrated Circuits, IC06 ...
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... The 74HC/HCT165 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. The 74HC/HCT165 are 8-bit parallel-load or serial-in shift registers with complementary serial outputs ( available from the last stage. When the parallel load ...
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... V) serial data input parallel data inputs 7 clock enable input (active LOW) positive supply voltage Fig.2 Logic symbol. 3 Product specification 74HC/HCT165 Fig.3 IEC logic symbol. ...
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... December 1990 Fig.4 Functional diagram. INPUTS Fig.5 Logic diagram. 4 Product specification 74HC/HCT165 Q REGISTERS OUTPUTS ...
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... Product specification 74HC/HCT165 . TEST CONDITIONS UNIT WAVEFORMS 125 (V) min. max. 250 ns 2.0 Fig.6 50 4.5 43 6.0 250 ns 2.0 Fig.6 50 4.5 43 6.0 180 ns 2.0 Fig.6 36 4.5 31 6.0 110 ns 2 ...
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... Product specification 74HC/HCT165 TEST CONDITIONS UNIT WAVEFORMS 125 (V) min. max 2.0 Fig.6 5 4 2.0 Fig.6 5 4.5 5 6.0 4 MHz 2.0 Fig.6 20 4.5 24 6.0 ...
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... The value of additional quiescent supply current ( I To determine I per input, multiply this value by the unit load coefficient shown in the table below. CC INPUT UNIT LOAD COEFFICIENT 0.65 CE 0.65 PL 0.65 December 1990 ) for a unit load given in the family specifications Product specification 74HC/HCT165 . ...
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... Product specification 74HC/HCT165 TEST CONDITIONS UNIT WAVEFORMS 125 ( 4.5 Fig 4.5 Fig 4.5 Fig 4.5 Fig 4.5 Fig 4.5 Fig 4.5 Fig ...
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... HCT 1 GND Fig.8 Waveforms showing the data input (D December 1990 propagation delays, the clock pulse width, the output ( Product specification 74HC/HCT165 propagation propagation delays when PL is LOW. 7 ...
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... HCT 1 GND Fig.10 Waveforms showing the set-up and hold times from the data inputs (D PACKAGE OUTLINES See “74HC/HCT/HCU/HCMOS Logic Package Outlines” December 1990 ) to the clock (CP) and clock the parallel load input (PL Product specification 74HC/HCT165 ...