74HC/HCT173 Philips Semiconductors (Acquired by NXP), 74HC/HCT173 Datasheet
74HC/HCT173
Related parts for 74HC/HCT173
74HC/HCT173 Summary of contents
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... DATA SHEET For a complete data sheet, please also download: The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications The IC06 74HC/HCT/HCU/HCMOS Logic Package Information The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines 74HC/HCT173 Quad D-type flip-flop; positive-edge trigger; 3-state Product specification File under Integrated Circuits, IC06 ...
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... Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. The 74HC/HCT173 are 4-bit parallel load registers with clock enable control, 3-state buffered outputs (Q and master reset (MR). When the two data enable inputs (E ...
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... LOW) 3-state flip-flop outputs clock input (LOW-to-HIGH, edge-triggered) ground (0 V) data enable inputs (active LOW) data inputs asynchronous master reset (active HIGH) positive supply voltage Fig.2 Logic symbol. 3 Product specification 74HC/HCT173 Fig.3 IEC logic symbol. ...
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... LOW-to-HIGH CP transition December 1990 Fig.4 Functional diagram. INPUTS INPUTS Q (register Product specification 74HC/HCT173 OUTPUTS (register OUTPUTS OE OE ...
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... Philips Semiconductors Quad D-type flip-flop; positive-edge trigger; 3-state December 1990 Fig.5 Logic diagram. 5 Product specification 74HC/HCT173 ...
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... Product specification 74HC/HCT173 . TEST CONDITIONS UNIT WAVEFORMS 125 (V) 265 ns 2.0 Fig.6 53 4.5 45 6.0 225 ns 2.0 Fig.7 45 4.5 38 6.0 225 ns 2.0 Fig.8 45 4.5 38 6.0 225 ns 2.0 Fig ...
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... Product specification 74HC/HCT173 TEST CONDITIONS UNIT WAVEFORMS 125 (V) ns 2.0 Fig.9 4.5 6.0 ns 2.0 Fig.9 4.5 6.0 MHz 2.0 Fig.6 4.5 6.0 ...
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... The value of additional quiescent supply current ( I To determine I per input, multiply this value by the unit load coefficient shown in the table below. CC INPUT December 1990 ) for a unit load given in the family specifications. CC UNIT LOAD COEFFICIENT 0.50 0.60 0.40 0.25 1.00 8 Product specification 74HC/HCT173 . ...
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... Product specification 74HC/HCT173 TEST CONDITIONS UNIT WAVEFORMS 125 ( 4.5 Fig 4.5 Fig 4.5 Fig 4.5 Fig 4.5 Fig.6 ns 4.5 Fig.6 ns 4.5 Fig.7 ns 4.5 Fig ...
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... 50 GND HCT 1 GND Fig.9 Waveforms showing the data set-up and hold times from input (En, D PACKAGE OUTLINES See “74HC/HCT/HCU/HCMOS Logic Package Outlines” 10 Product specification 74HC/HCT173 . ) clock (CP ...