ak2548 AKM Semiconductor, Inc., ak2548 Datasheet
ak2548
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ak2548 Summary of contents
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... Channel E1 Transceiver Block Diagram C0028-E-00 7 channel E1 Transceiver FEATURE BLOCK DIAGRAM CONTROL LOS RECOVER SHAPER 1 [AK2548] AK2548 R /W (WR) AD7-AD0 AS(ALE ...
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... ASAHI KASEI The AK2548 is the 7 channel E1 transceiver for a SDH/SONET MUX, M13 MUX, etc. It includes seven independent transmitters, clock and data recovery, LOS detector, control circuit in one LQFP-144 package which saves space, power consumption and the board design time. Internally generated transmit pulse provides the appropriate pulse shape. ...
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... Power Power Power Power CMOS CMOS CMOS CMOS 15pF CMOS 15pF CMOS 15pF Power Power Power CMOS 15pF CMOS 15pF CMOS 15pF CMOS 50pF CMOS 50pF CMOS 50pF CMOS 50pF CMOS 50pF CMOS 50pF CMOS 50pF CMOS 50pF 3 [AK2548] Comments 1999/9 ...
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... Power Power CMOS Analog Analog CMOS Analog Analog CMOS Analog Analog CMOS Power Analog 12k Power CMOS Analog Analog CMOS Analog Analog CMOS Analog Analog CMOS Analog Analog Power 4 [AK2548] Comments PMOS open drain Note 1 Note 1 ±1% accuracy Note 1 Note 1 1999/9 ...
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... CMOS CMOS CMOS Power Power Power CMOS 15pF CMOS 15pF CMOS 15pF CMOS CMOS CMOS Power Power Power Power CMOS 15pF CMOS 15pF CMOS 15pF CMOS CMOS CMOS CMOS 15pF CMOS 15pF CMOS 15pF CMOS CMOS CMOS 5 [AK2548] Comments 1999/9 ...
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... Power Analog Power Analog Power Power Analog Power Analog Power Power Analog Power 6 [AK2548] Comments driver output driver output driver output driver output driver output driver output driver output driver output driver output driver output driver output driver output driver output ...
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... Bus Type Select Input BTS=“H” : Motorola Mode BTS=“L” : Intel Mode SCLK I Serial Clock Input SDI I Serial Data Input SDO O Serial Data Output AD0-AD7 I/O Address/Data Input/Output Used for read/write internal registers. C0028-E-00 PIN FUNCTION Function 7 [AK2548] Comment 1999/9 ...
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... Positive Power Supply for Reference Circuit BVSS Negative Power Supply for Reference Circuit PVDD Positive Power Supply for PLL PVSS Negative Power Supply for PLL BGREF Bandgap Reference Output. 12k ± 1% exeternal register should be connected across this pin and VSS. C0028-E-00 Function 8 [AK2548] Comment 1999/9 ...
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... V+ 3.135 3.3 3.465 Ta -40 25 +85 Symbol min typ VOH 0.9VDD VOL VIH 0.7VDD VIL 0.3VDD Ii IOH 1.0 9 [AK2548] Units Condition V V Apply to except for RTIPx, RRINGx V Apply to RTIPx, RRINGx mA ºC Units Condition V 3.3V±5% ºC max Units Condition 160 mW Note1 147 mW V IOH=-40µA ...
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... Note4: PN15 pattern input. Jitter Tolerance(G.823) 36.9 1.5 0.2 1.2× C0028-E-00 ±10%@75 system, 0p Symbol Min Typ Max Units 5 -6 0.28 0.4 0.55 0.35 0.5 0.7 170 175 180 12 16 nspp Note4 1/16 Mark ITU-T G.823 2.4kHz 18kHz 100kHz 20Hz Jitter Frequency 10 [AK2548] Condition k dB Note1 V Note2 V bits dB Note3 1999/9 ...
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... Max 2. 2.60 2.7 3.0 3.3 -0.237 0. 237 -0 269 ns (244 + 25) 194 ns (244 – 50) Nominal pulse 244 ns 219 ns (244 – 25) 488 ns (244 + 244) Note – V corresponds to the nominal peak value. 11 [AK2548] Units Condition G.703 V Note Note UIpp 1999/9 ...
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... RPOS t h1 RNEG TCLK t 50 su2 TPOS t h2 TNEG RCLK t r RPOS RNEG TCLK t f TPOS TNEG ))×100% 12 [AK2548] Max Units Condition 2.048204 MHz ±100ppm 32.77127 MHz ns Refer to Fig.2 ns Refer to Fig.1 % Note1 ns Refer to Fig.1 ns Refer to Fig.2 100 ns Refer to Fig.3 Note2 40 ns Refer to Fig ...
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... ASAHI KASEI t pwho 50% RCLK RPOS/RNEG Figure 1. Receiver Timing t pwhi 50% TCLK t sut TPOS/TNEG 50% Figure 2. Transmitter Timing t r 10% Figure 3. Rise and Fall Times (RCLK,RPOS,RNEG,TCLK,TPOS,TNEG) C0028-E-00 t pwlo 50% 50 sur hr 50% t pwli 50% 50 90% 90% 10% 13 [AK2548] 1999/9 ...
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... Units Condition ...
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... ASAHI KASEI Motorola Mode(READ t14 AS t1 AD7-0 Address R/W Motorola Mode(WRITE t14 AS t1 AD7-0 Address R/W C0028-E-00 t9 t10 t13 Data t15 t7 t8 t10 t9 t13 t11 t12 Data [AK2548] t4 1999/9 ...
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... ASAHI KASEI Intel Mode(READ t34 ALE t21 AD7-0 Address RD Intel Mode(WRITE t34 ALE t21 AD7-0 Address RD C0028-E-00 t28 t29 t25 t26 t22 t27 Data t35 t32 t29 t28 t33 t23 t24 t22 t30 t31 Data 16 [AK2548] 1999/9 ...
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... Tp8 20 — — tp9 100 — — tp10 tp11 — — MSB tp10 tp6 17 [AK2548] Units Condition — ns — ns — ns — — ns — ns — tp9 tp8 tp8 16 tp11 8 High-Z ...
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... RLOOP4 LLOOP4 (0) (0) (0) (0) EC5 RLOOP5 LLOOP5 (0) (0) (0) (0) EC6 RLOOP6 LLOOP6 (0) (0) (0) (0) EC7 RLOOP7 LLOOP7 (0) (0) (0) (0) 18 [AK2548] Bit2 Bit1 Bit0 <AD2> <AD1> <AD0> LOS2 LOS1 0 (1) (1) LOTC2 LOTC1 LOMC (1) (1) (1) MLOS2 MLOS1 RDEN (1) (1) (0) MLOTC2 MLOTC1 MLOMC (1) (1) ...
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... TAOS is active-high to output all one’s signal from TTIPx and TRINGx. TAOSx All one’s signal synchronized with TCLK. When TCLK is lost, the signal synchronized with MCLK. Application is selected by this register in Table 3. ECx C0028-E-00 Description Description Description Initial value is low. 19 [AK2548] 1999/9 ...
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... Table 2. TIPx/RINGx Polarity Control POLNx POSx/NEGx Table 3 Equalizer Control ECx Application 0 E1-Coax( E1-Twisted Pair(120 ) C0028-E-00 Function Normal (Initial value) Local Loop back Remote Loop back Inhibited TIPx/RINGx space mark mark space (Initial value) 20 [AK2548] 1999/9 ...
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... Clocked loss 1 1 Loss loss 0 * Clocked Clocked loss 0 * Loss Loss loss 0 1 clocked loss 0 1 loss loss 21 [AK2548] TTIP RCLK RPOS LOS TRING RNEG * TTIP RCLK RPOS ...
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... All Mark * clocked in All Mark 0 clocked loss All Mark * loss in All Mark 0 loss loss All Mark 1 clocked loss All Mark 1 loss loss All Mark 22 [AK2548] RCLK RPOS LOS RNEG RCLK RTIP 0 RRING RCLK RTIP 0 RRING RCLK RTIP 1 RRING RCLK RTIP 1 ...
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... Receive TTIP signal TRING * * in All Mark 0 * loss All Mark 1 * loss All Mark * * in All Mark 0 * loss All Mark 1 * loss All Mark 23 [AK2548] RCLK RPOS LOS RNEG RCLK RTIP 0 RRING RCLK RTIP 1 RRING RCLK RTIP 0 RRING RCLK RTIP 1 RRING RCLK RPOS ...
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... All Mark * loss loss All Mark * clocked in All Mark * clocked loss All Mark * loss in All Mark * loss loss All Mark 24 [AK2548] RCLK RPOS LOS RNEG TCLK TPOS 0 (Note) TNEG TCLK TPOS 1 (Note) TNEG TCLK TPOS 0 (Note) TNEG ...
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... MCLK from setting INT output. INT output INT output goes “high” when the alarm is reported to any one of LOSx, LOTCx or LOMC registers. This pin can be masked by MLOSx, MLOTCx or MLOMC registers. C0028-E-00 THEORY OF OPERATION 25 [AK2548] 1999/9 ...
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... When BTS is set to “ high”, Motorola mode is selected. When BTS is set to “ low”, Intel mode is selected. Serial Interface The timing of serial interface is shown below. CS SCLK SDI R High-Z SDO R/W=1: read R/W=0: write C0028-E-00 When P/S is set to “low”, parallel [AK2548] 1999/9 ...
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... Tx 75 1:2 720uH 120 1:2.2 720uH Rx 1:2 1.2mH C0028-E-00 1 120 1:2 1:2.2 8.2 ±1% 9.1 ±1% 1uF 1uF 470pF 470pF 2 120 20 82 130 160 100 Leakage Interwinding Inductance Capacitance (Max) (Max) 0.3uH 30pF 0.3uH 30pF 0.3uH 30pF 27 [AK2548] DCR (Max) pri sec 0.6 1.2 0.6 1.3 0.6 1.2 1999/9 ...
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... AK2548 BGREF Power Supply To attenuate the power supply noise, connect capacitors between VDD and VSS respectively. The value of the capacitance AK2548 need depend on the condition of the power supply line. Please decide the value of the capacitance after your evaluation. AK2548 Pin name ...
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... ASAHI KASEI 144pin LQFP OUTPUT DIMENSIONS 22.0 20.0 108 109 AK2548 XXXXXXX JAPAN 144 1 0.50 0.10 C0028-E-00 PACKAGE 0.10 M 0.20 0.50±0.1 29 [AK2548] 0~10° 1999/9 ...
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... AKM harmless from any and all claims arising from the use of said product in the absence of such notification. C0028-E-00 IMPORTANT NOTICE 30 [AK2548] Before considering As 1999/9 ...