January 1996
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
http://www.intersil.com or 407-727-9207
Features
• Devices QML Qualified in Accordance with MIL-PRF-38535
• Detailed Electrical and Screening Requirements are Contained in
• 1.25 Micron Radiation Hardened SOS CMOS
• Total Dose . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . >300K RAD (Si)
• Single Event Upset (SEU) Immunity: <1 x 10
• SEU LET Threshold . . . . . . . . . . . . . . . . . . . . . . . >100 MEV-cm
• Dose Rate Upset . . . . . . . . . . . . . . . . >10
• Dose Rate Survivability . . . . . . . . . . . >10
• Latch-Up Free Under Any Conditions
• Military Temperature Range . . . . . . . . . . . . . . . . . . -55
• Significant Power Reduction Compared to ALSTTL Logic
• DC Operating Voltage Range . . . . . . . . . . . . . . . . . . . . 4.5V to 5.5V
• Input Logic Levels
• Input Current
• Fast Propagation Delay . . . . . . . . . . . . . . . . 21ns (Max), 14ns (Typ)
Description
The Intersil ACS161MS is a Radiation Hardened 4-Bit Binary Synchronous
Counter. The MR is an active low master reset. SPE is an active low
Synchronous Parallel Enable which disables counting and allows data at the
preset inputs (P0 - P3) to load the counter. CP is the positive edge clock. TC is
the terminal count or carry output. Both TE and PE must be high for counting
to occur, but are irrelevant to loading. TE low will keep TC low.
The ACS161MS utilizes advanced CMOS/SOS technology to achieve
high-speed operation. This device is a member of a radiation hardened,
high-speed, CMOS/SOS Logic family.
The ACS161MS is supplied in a 16 lead Ceramic Flatpack (K suffix) or a
Ceramic Dual-In-Line Package (D suffix).
Ordering Information
5962F9670601VEC
5962F9670601VXC
ACS161D/Sample
ACS161K/Sample
ACS161HMSR
SMD# 5962-96706 and Intersil’ QM Plan
(Typ)
- VIL = 30% of VCC Max
- VIH = 70% of VCC Min
PART NUMBER
1 A at VOL, VOH
|
TEMPERATURE RANGE
Copyright
-55
-55
o
o
C to +125
C to +125
25
25
25
©
o
o
o
Intersil Corporation 1999
C
C
C
11
12
o
o
C
C
RAD (Si)/s, 20ns Pulse
RAD (Si)/s, 20ns Pulse
-10
MIL-PRF-38535 Class V
MIL-PRF-38535 Class V
Sample
Sample
Die
Errors/Bit/Day
o
C to +125
1
SCREENING LEVEL
2
/mg
o
C
ACS161MS
Pinouts
GND
MIL-STD-1835, DESIGNATOR CDFP4-F16,
MR
MIL-STD-1835, DESIGNATOR CDIP2-T16,
CP
PE
P0
P1
P2
P3
4-Bit Synchronous Counter
16 PIN CERAMIC DUAL-IN-LINE
GND
16 PIN CERAMIC FLATPACK
MR
CP
PE
P0
P1
P2
P3
1
2
3
4
5
6
7
8
16 Lead SBDIP
16 Lead Ceramic Flatpack
16 Lead SBDIP
16 Lead Ceramic Flatpack
Die
LEAD FINISH C
LEAD FINISH C
1
2
3
4
5
6
7
8
Radiation Hardened
TOP VIEW
TOP VIEW
Spec Number
PACKAGE
File Number
16
15
14
13
12
11
10
9
16
15
14
13
12
11
10
9
VCC
TC
Q0
Q1
Q2
Q3
TE
SPE
518818
VCC
TC
Q0
Q1
Q2
Q3
TE
SPE
3600.1