MC14011UBCPG ON Semiconductor, MC14011UBCPG Datasheet

IC GATE NAND QUAD CMOS 14DIP

MC14011UBCPG

Manufacturer Part Number
MC14011UBCPG
Description
IC GATE NAND QUAD CMOS 14DIP
Manufacturer
ON Semiconductor
Series
4000Br
Datasheet

Specifications of MC14011UBCPG

Logic Type
NAND Gate
Number Of Inputs
2
Number Of Circuits
4
Current - Output High, Low
3.4mA, 3.4mA
Voltage - Supply
3 V ~ 18 V
Operating Temperature
-55°C ~ 125°C
Mounting Type
Through Hole
Package / Case
14-DIP (0.300", 7.62mm)
Output Current
8.8mA
No. Of Inputs
2
Supply Voltage Range
3V To 18V
Logic Case Style
DIP
No. Of Pins
14
Operating Temperature Range
-55°C To +125°C
Filter Terminals
DIP
Rohs Compliant
Yes
Family Type
4000 CMOS
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
MC14011UBCPGOS

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
MC14011UBCPG
Manufacturer:
ON/安森美
Quantity:
20 000
MC14001UB, MC14011UB
UB-Suffix Series
CMOS Gates
enhancement mode devices in a single monolithic structure
(Complementary MOS). Their primary use is where low power
dissipation and/or high noise immunity is desired. The UB set of
CMOS gates are inverting non−buffered functions.
Features
Stresses exceeding Maximum Ratings may damage the device. Maximum
Ratings are stress ratings only. Functional operation above the Recommended
Operating Conditions is not implied. Extended exposure to stresses above the
Recommended Operating Conditions may affect device reliability.
1. Temperature Derating:
static voltages or electric fields. However, precautions must be taken to avoid
applications of any voltage higher than maximum rated voltages to this
high−impedance circuit. For proper operation, V
to the range V
(e.g., either V
MAXIMUM RATINGS
© Semiconductor Components Industries, LLC, 2009
September, 2009 − Rev. 7
Symbol
V
I
The UB Series logic gates are constructed with P and N channel
This device contains protection circuitry to guard against damage due to high
Unused inputs must always be tied to an appropriate logic voltage level
in
in
Low−Power Schottky TTL Load Over the Rated Temperature Range
Suffix Devices
Supply Voltage Range = 3.0 Vdc to 18 Vdc
Linear and Oscillator Applications
Capable of Driving Two Low−Power TTL Loads or One
Double Diode Protection on All Inputs
Pin−for−Pin Replacements for Corresponding CD4000 Series UB
These are Pb−Free Devices
V
T
Plastic “P and D/DW” Packages: – 7.0 mW/_C From 65_C To 125_C
P
, V
, I
T
T
stg
DD
D
A
L
out
out
DC Supply Voltage Range
Input or Output Voltage Range
Input or Output Current
Power Dissipation, per Package
Ambient Temperature Range
Storage Temperature Range
Lead Temperature
SS
SS
(DC or Transient)
(DC or Transient) per Pin
(Note 1)
(8−Second Soldering)
or V
v (V
DD
in
). Unused outputs must be left open.
Parameter
or V
(Voltages Referenced to V
out
) v V
DD
.
in
and V
−0.5 to V
SS
−0.5 to +18.0
−55 to +125
−65 to +150
out
)
Value
± 10
500
260
should be constrained
DD
+ 0.5
1
Unit
mW
mA
°C
°C
°C
V
V
See detailed ordering and shipping information in the package
dimensions section on page 4 of this data sheet.
xx
A
WL, L
YY, Y
WW, W
G
ORDERING INFORMATION
http://onsemi.com
CASE 751A
= Specific Device Code
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
D SUFFIX
SOIC−14
CASE 646
P SUFFIX
PDIP−14
Publication Order Number:
14
1
14
1
MC140xxUBCP
DIAGRAMS
AWLYYWWG
MARKING
MC14001UB/D
AWLYWW
140xxUG

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MC14011UBCPG Summary of contents

Page 1

MC14001UB, MC14011UB UB-Suffix Series CMOS Gates The UB Series logic gates are constructed with P and N channel enhancement mode devices in a single monolithic structure (Complementary MOS). Their primary use is where low power dissipation and/or high noise immunity ...

Page 2

LOGIC DIAGRAMS MC14001UB Quad 2−Input NOR Gate FOR ALL DEVICES PIN ASSIGNMENTS MC14001UB Quad 2−Input NOR Gate ...

Page 3

ELECTRICAL CHARACTERISTICS Î Î Î Î Î ...

Page 4

... ORDERING INFORMATION Device MC14001UBCPG MC14001UBDG MC14001UBDR2G MC14011UBCPG MC14011UBDG MC14011UBDR2G †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/ INPUT PULSE GENERATOR * *All unused inputs of AND, NAND gates must be connected to V ...

Page 5

MC14001UB CIRCUIT SCHEMATIC Vdc 25° Unused input 14 connected One input only ...

Page 6

−T− SEATING PLANE 0.13 (0.005) PACKAGE DIMENSIONS PDIP−14 CASE 646−06 ISSUE http://onsemi.com 6 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI ...

Page 7

... Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein ...

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