S25FL016A0LMAI000 SPANSION [SPANSION], S25FL016A0LMAI000 Datasheet - Page 21

• Manufacturer Part Number: S25FL016A0LMAI000
• Description: 16 Megabit CMOS 3.0 Volt Flash Memory with 50MHz SPI (Serial Peripheral Interface) Bus
• Manufacturer: SPANSION [SPANSION]

9.9
August 28, 2006 S25FL016A_00_C0
Sector Erase (SE)
The Sector Erase (SE) command sets all bits at all addresses within a specified sector to a logic 1. A WREN
command is required prior to writing the PP command.
The host system must drive CS# low, and then write the SE command plus three address bytes on SI. Any
address within the sector (see
driven low for the entire duration of the SE sequence. The command sequence is shown in
Table
The host system must drive CS# high after the device has latched the 8th bit of the SE command, otherwise
the device does not execute the command. The SE operation begins as soon as CS# is driven high. The
device internally controls the timing of the operation, which requires a period of t
be read to check the value of the Write In Progress (WIP) bit while the SE operation is in progress. The WIP
bit is 1 during the SE operation, and is 0 when the operation is completed. The device internally resets the
Write Enable Latch to 0 before the operation completes (the exact timing is not specified).
The device does not execute an SE command that specifies a sector that is protected by the Block Protect
bits (BP2:BP0) (see
SCK
CS#
9.4.
SCK
SI
CS#
CS#
SCK
SI
SO
SI
Mode 3
Mode 0
D a t a
Hi-Z
Mode 3
Mode 0
MSB
40
7
41
6
Table 7.1 on page
42
5
Data Byte 2
S h e e t
0
43
4
1
0
44
3
Figure 9.8 Page Program (PP) Command Sequence
Figure 9.9 Sector Erase (SE) Command Sequence
2
Command
2
45
Table 7.1 on page
1
3
1
46
( P r e l i m i n a r y )
4
2
0
Command
47 48 49 50 51 52 53 54 55
5
7
MSB
11).
3
S25FL016A
6
6
4
7
5
23 22 21
MSB
8
Data Byte 3
5
4
11) is a valid address for the SE command. CS# must be
9
3
6
24-Bit Address
10
2
7
MSB
1
23 22
3
28
8
0
2
29
9
1
24-bit Address
21
30
10
MSB
0
7
31
MSB
7
6
32
28
6
3
5
Data Byte 256
33
29
5
4
2
34
Data Byte 1
4
SE
3
30
35 36 37 38 39
1
. The Status Register may
3
2
31
0
2
1
1
0
Figure 9.9
0
and
19