S25FL016A0LMAI000 SPANSION [SPANSION], S25FL016A0LMAI000 Datasheet - Page 22

• Manufacturer Part Number: S25FL016A0LMAI000
• Description: 16 Megabit CMOS 3.0 Volt Flash Memory with 50MHz SPI (Serial Peripheral Interface) Bus
• Manufacturer: SPANSION [SPANSION]

9.10
9.11
20
Bulk Erase (BE)
Deep Power Down (DP)
The Bulk Erase (BE) command sets all the bits within the entire memory array to logic 1s. A WREN command
is required prior to writing the PP command.
The host system must drive CS# low, and then write the BE command on SI. CS# must be driven low for the
entire duration of the BE sequence. The command sequence is shown in
The host system must drive CS# high after the device has latched the 8th bit of the CE command, otherwise
the device does not execute the command. The BE operation begins as soon as CS# is driven high. The
device internally controls the timing of the operation, which requires a period of t
be read to check the value of the Write In Progress (WIP) bit while the BE operation is in progress. The WIP
bit is 1 during the BE operation, and is 0 when the operation is completed. The device internally resets the
Write Enable Latch to 0 before the operation completes (the exact timing is not specified).
The device only executes a BE command if all Block Protect bits (BP2:BP0) are 0 (see
Otherwise, the device ignores the command.
The Deep Power Down (DP) command provides the lowest power consumption mode of the device. It is
intended for periods when the device is not in active use, and ignores all commands except for the Release
from Deep Power Down (RES) command. The DP mode therefore provides the maximum data protection
against unintended write operations. The standard standby mode, which the device goes into automatically
when CS# is high (and all operations in progress are complete), should generally be used for the lowest
power consumption when the quickest return to device activity is required.
The host system must drive CS# low, and then write the DP command on SI. CS# must be driven low for the
entire duration of the DP sequence. The command sequence is shown in
The host system must drive CS# high after the device has latched the 8th bit of the DP command, otherwise
the device does not execute the command. After a delay of t
reduces from I
Once the device has entered the DP mode, all commands are ignored except the RES command (which
releases the device from the DP mode). The RES command also provides the Electronic Signature of the
device to be output on SO, if desired (see sections
DP mode automatically terminates when power is removed, and the device always powers up in the standard
standby mode. The device rejects any DP command issued while it is executing a program, erase, or Write
Status Register operation, and continues the operation uninterrupted.
SB
to I
SO
CS#
SCK
SI
DP
(see
Hi-Z
Mode 3
Mode 0
Figure 9.10 Bulk Erase (BE) Command Sequence
Table 14.1 on page
D a t a
S25FL016A
S h e e t
0
1
24).
9.12
2
( P r e l i m i n a r y )
Command
3
and 9.12.1).
DP,
4
the device enters the DP mode and current
5
6
Figure 9.10
Figure 9.11
7
BE
S25FL016A_00_C0 August 28, 2006
. The Status Register may
and
and
Table 7.1 on page
Table
Table
9.4.
9.4.
11).