SST25VF040-20-4C-QAE SST [Silicon Storage Technology, Inc], SST25VF040-20-4C-QAE Datasheet

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SST25VF040-20-4C-QAE

Manufacturer Part Number
SST25VF040-20-4C-QAE
Description
4 Mbit SPI Serial Flash
Manufacturer
SST [Silicon Storage Technology, Inc]
Datasheet
FEATURES:
• Single 2.7-3.6V Read and Write Operations
• Serial Interface Architecture
• 20 MHz Max Clock Frequency
• Superior Reliability
• Low Power Consumption:
• Flexible Erase Capability
• Fast Erase and Byte-Program:
• Auto Address Increment (AAI) Programming
PRODUCT DESCRIPTION
The SST serial flash family features a four-wire, SPI-
compatible interface that allows for a low pin-count pack-
age occupying less board space and ultimately lowering
total system costs. SST25VF040 SPI serial flash memo-
ries are manufactured with SST proprietary, high perfor-
mance CMOS SuperFlash Technology. The split-gate
cell design and thick-oxide tunneling injector attain better
reliability and manufacturability compared with alternate
approaches.
The SST25VF040 device significantly improves perfor-
mance, while lowering power consumption. The total
energy consumed is a function of the applied voltage, cur-
©2006 Silicon Storage Technology, Inc.
S71231(04)-01-EOL
1
– SPI Compatible: Mode 0 and Mode 3
– Endurance: 100,000 Cycles (typical)
– Greater than 100 years Data Retention
– Active Read Current: 7 mA (typical)
– Standby Current: 8 µA (typical)
– Uniform 4 KByte sectors
– Uniform 32 KByte overlay blocks
– Chip-Erase Time: 70 ms (typical)
– Sector- or Block-Erase Time: 18 ms (typical)
– Byte-Program Time: 14 µs (typical)
– Decrease total chip programming time over
Byte-Program operations
SST25VF020 / 0402Mb / 4Mb Serial Peripheral Interface (SPI) flash memory
09/10
4 Mbit SPI Serial Flash
SST25VF040
The SST logo and SuperFlash are registered Trademarks of Silicon Storage Technology, Inc.
• End-of-Write Detection
• Hold Pin (HOLD#)
• Write Protection (WP#)
• Software Write Protection
• Temperature Range
• Packages Available
• All non-Pb (lead-free) devices are RoHS compliant
rent, and time of application. Since for any given voltage
range, the SuperFlash technology uses less current to
program and has a shorter erase time, the total energy
consumed during any Erase or Program operation is less
than alternative flash memory technologies. The
SST25VF040 device operates with a single 2.7-3.6V
power supply.
The SST25VF040 device is offered in an 8-lead SOIC 200
mil body width (S2A) package and in an 8-contact WSON
package. See Figure 2 for the pin assignments.
– Software Status
– Suspends a serial sequence to the memory
– Enables/Disables the Lock-Down function of the
– Write protection through Block-Protection bits in
– Commercial: 0°C to +70°C
– Industrial: -40°C to +85°C
– Extended: -20°C to +85°C
– 8-lead SOIC 200 mil body width
– 8-contact WSON (5mm x 6mm)
without deselecting the device
status register
status register
These specifications are subject to change without notice.
EOL Product Data Sheet

Related parts for SST25VF040-20-4C-QAE

SST25VF040-20-4C-QAE Summary of contents

Page 1

... The SST25VF040 device operates with a single 2.7-3.6V power supply. The SST25VF040 device is offered in an 8-lead SOIC 200 mil body width (S2A) package and in an 8-contact WSON package. See Figure 2 for the pin assignments. The SST logo and SuperFlash are registered Trademarks of Silicon Storage Technology, Inc. ...

Page 2

... EOL Product Data Sheet Address Buffers and Latches CE# FIGURE 1: Functional Block Diagram ©2006 Silicon Storage Technology, Inc Decoder Control Logic Serial Interface SCK SI SO WP# HOLD Mbit SPI Serial Flash SST25VF040 SuperFlash Memory Y - Decoder I/O Buffers and Data Latches 1231 B1.0 S71231(04)-01-EOL 09/10 ...

Page 3

... Mbit SPI Serial Flash SST25VF040 PIN DESCRIPTION CE Top View WP 1231 08-soic P1.0 8- SOIC LEAD FIGURE 2: Pin Assignments TABLE 1: Pin Description Symbol Pin Name Functions SCK Serial Clock To provide the timing of the serial interface. Commands, addresses, or input data are latched on the rising edge of the clock input, while output data is shifted out on the falling edge of the clock input ...

Page 4

... BFH Data Input (SI), Serial Data Output (SO), and Serial Clock (SCK). 44H The SST25VF040 supports both Mode 0 (0,0) and Mode 3 T2.0 1231(04) (1,1) of SPI bus operations. The difference between the two modes, as shown in Figure 3, is the state of the SCK signal when the bus master is in Stand-by mode and no data is being transferred ...

Page 5

... HOLD# Active FIGURE 4: Hold Condition Waveform Write Protection SST25VF040 provides software Write protection. The Write Protect pin (WP#) enables or disables the lock-down function of the status register. The Block-Protection bits (BP1, BP0, and BPL) in the status register provide Write protection to the memory array and the status register. See Table 5 for Block-Protection description ...

Page 6

... Silicon Storage Technology, Inc. 4 Mbit SPI Serial Flash Program operation, the status register may be read only to determine the completion of an operation in progress. Table 4 describes the function of each bit in the software status register. Default at Power- SST25VF040 Read/Write R R R/W R/W N/A R R/W T4.0 1231(04) S71231(04)-01-EOL 09/10 ...

Page 7

... Mbit SPI Serial Flash SST25VF040 Block Protection (BP1, BP0) The Block-Protection (BP1, BP0) bits define the size of the memory area, as defined in Table software pro- tected against any memory Write (Program or Erase) operations. The Write-Status-Register (WRSR) instruction is used to program the BP1 and BP0 bits as long as WP# is high or the Block-Protect-Lock (BPL) bit is 0 ...

Page 8

... EOL Product Data Sheet Instructions Instructions are used to Read, Write (Erase and Program), and configure the SST25VF040. The instruction bus cycles are 8 bits each for commands (Op Code), data, and addresses. Prior to executing any Byte-Program, Auto Address Increment (AAI) programming, Sector-Erase, Block-Erase, or Chip-Erase instructions, the Write-Enable (WREN) instruction must be executed first ...

Page 9

... Mbit SPI Serial Flash SST25VF040 Read The Read instruction outputs the data starting from the specified address location. The data output stream is con- tinuous through all addresses until terminated by a low to high transition on CE#. The internal address pointer will automatically increment until the highest memory address is reached ...

Page 10

... Write Disable (WRDI) Instruction to terminate AAI Operation 10 4 Mbit SPI Serial Flash SST25VF040 for the completion of each inter Data Byte 2 05 Read Status Register (RDSR) ...

Page 11

... Mbit SPI Serial Flash SST25VF040 Sector-Erase The Sector-Erase instruction clears all bits in the selected 4 KByte sector to FFH. A Sector-Erase instruction applied to a protected memory area will be ignored. Prior to any Write operation, the Write-Enable (WREN) instruction must be executed. CE# must remain active low for the duration of the any command sequence ...

Page 12

... CE#. See Figure 11 for the RDSR instruction sequence Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 MSB 12 4 Mbit SPI Serial Flash SST25VF040 Status 1231 F10.1 Register Out S71231(04)-01-EOL for CE 09/10 ...

Page 13

... Mbit SPI Serial Flash SST25VF040 Write-Enable (WREN) The Write-Enable (WREN) instruction sets the Write- Enable-Latch bit to 1 allowing Write operations to occur. The WREN instruction must be executed prior to any Write (Program/Erase) operation. CE# must be driven high before the WREN instruction is executed. FIGURE 12: Write Enable (WREN) Sequence ...

Page 14

... WRSR instruction is executed. See Figure 14 for EWSR and WRSR instruction sequences MODE 3 MODE 0 STATUS REGISTER MSB MSB HIGH IMPEDANCE 14 SST25VF040 1231 F13.1 S71231(04)-01-EOL 09/10 ...

Page 15

... Mbit SPI Serial Flash SST25VF040 Read-ID The Read-ID instruction identifies the devices as SST25VF040 and manufacturer as SST. The device infor- mation can be read from executing an 8-bit command, 90H or ABH, followed by address bits [A Read-ID instruction, the manufacturer’ located in CE# MODE ...

Page 16

... V =GND to V OUT =100 µ -0 =-100 µ Mbit SPI Serial Flash SST25VF040 +0.5V DD +2. EST = /0.9 V @20 MHz, SO=open Max Max Min ...

Page 17

... Mbit SPI Serial Flash SST25VF040 TABLE 10: Reliability Characteristics Symbol Parameter 1 N Endurance END 1 T Data Retention Latch Up LTH 1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter. TABLE 11: AC Operating Characteristics V Symbol ...

Page 18

... FIGURE 18: Hold Timing Diagram ©2006 Silicon Storage Technology, Inc. T SCKF T SCKR T SCKL T OH MSB HHH HLS T HLH Mbit SPI Serial Flash SST25VF040 T CPH T T CEH CHS LSB HIGH-Z 1231 F15.0 T CHZ LSB 1231 F16.0 T HHS T LZ 1231 F17.0 S71231(04)-01-EOL 09/10 ...

Page 19

... Mbit SPI Serial Flash SST25VF040 Max DD Chip selection is not allowed. All commands are rejected by the device. V Min DD FIGURE 19: Power-up Timing Diagram ©2006 Silicon Storage Technology, Inc. EOL Product Data Sheet T PU-READ Device fully accessible T PU-WRITE 19 Time 1231 F18.0 S71231(04)-01-EOL ...

Page 20

... V (0.1V DD ILT DD ) and V (0.3V ). Input rise and fall times (10 TESTER TO DUT 20 4 Mbit SPI Serial Flash SST25VF040 V HT OUTPUT V LT 1231 F19.1 ) for a logic “0”. Measurement reference points ↔ 90%) are <5 ns. Note Test HT HIGH ...

Page 21

... Suffix1 SST25VFXXX - XXX - XX Valid combinations for SST25VF040 SST25VF040-20-4C-S2AE SST25VF040-20-4C-QAE SST25VF040-20-4I-S2AE SST25VF040-20-4I-QAE SST25VF040-20-4E-S2AE SST25VF040-20-4E-QAE Note: Valid combinations are those products in mass production or will be in mass production. Consult your SST sales representative to confirm availability of valid combinations and to determine availability of new combinations. ...

Page 22

... Maximum allowable mold flash is 0. the package ends and 0.25 mm between leads. FIGURE 22: 8-lead Small Outline Integrated Circuit (SOIC) 200 mil body width (5.2mm x 8mm) SST Package Code: S2A ©2006 Silicon Storage Technology, Inc. 4 Mbit SPI Serial Flash SIDE VIEW 0.50 0.35 1.27 BSC 0.25 END VIEW 0.05 2.16 1.75 0.25 0.19 08-soic-EIAJ-S2A-3 22 SST25VF040 0° 8° 0.80 0.50 1mm S71231(04)-01-EOL 09/10 ...

Page 23

... Connection of this paddle to any other voltage potential can result in shorts and/or electrical malfunction of the device. FIGURE 23: 8-contact Very-very-thin Small Outline No-lead (WSON) SST Package Code: QA TABLE 12: Revision History Number • Initial release of S71231(04) EOL of SST25VF040 00 01 • Fixed Title and Figures 16-20 ©2006 Silicon Storage Technology, Inc. SIDE VIEW ...

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