mn3672re Panasonic Corporation of North America, mn3672re Datasheet - Page 5

• Manufacturer Part Number: mn3672re
• Description: Color Ccd Linear Image Sensor With 5000 Bits Each For R, G, And B Colors
• Manufacturer: Panasonic Corporation of North America

CCD Linear Image Sensor
Note 7) Dynamic range (DR)
Note 8) The signal output pin DC level (V
The MN3672 can be made up of the three sections of—a)
photo detector region, b) CCD transfer region (shift register),
and c) output region.
a) Photo detector region
b) CCD Transfer region (analog shift register)
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floating photodiode and a 3µm channel stopper (isolation
region) per pixel, and 5000 pixels' lines of each of the colors
R, G, and B are arranged neighboring.
scanning direction (center to center spacing of 14µm) and a
similar one line spacing between R-G in the sideways
scanning direction (center to center spacing of 14µm).
(Horizontal)
photodetector window are optically shielded.
reference) pixels for each color that can be used as the black
level reference.
transferred to the CCD transfer regions of the respective
colors during the period when the shift gate (ø
High level. The signal charges transferred to this analog shift
register are successively transferred to the output region.
(ø
The photodetector window is a rectangle of dimensions 8µm
A buried type CCD that can be driven by a two phase clock
There is a spacing of one line between B-R in the sideways
The signal charges obtained by photoelectric conversion are
In the CCD transfer region, since each CCD shift register is
Optical Characteristics (continued)
The photoelectric conversion device consists of an 11µm
The photodetector region has 24 optically shielded (black
Construction of the Image Sensor
1
, ø
2
) is used for the analog shift register.
This is defined by the following equation.
Since the dark signal output voltage is proportional to the accumulation time, the dynamic range becomes wider when the
accumulation time is shorter.
following figure.
DR= V
OS
OS
OS
waveform
V
SS
1
2
3
11µm (Vertical), and the areas other than the
V
SAT
DRK
V
OS
Reset feed
through level
OS
) and the compensation output pin DC level (V
SG
) is at the
DS waveform
V
SS
c) Output region
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divided into four segments each of which are provided with
separate ø
generation in the chip and the load on the clock driver circuit
by providing separate clock driver circuit for each pin during
high speed operation.
independent pin (ø
other pins by a clock driver, it is possible to speed up the
flow of signal charge into the charge to voltage conversion
region thereby making the output waveform rise sharply.
This makes it easy to obtain margin of the signal processing
time during high speed drive operation.
to the charge to voltage conversion region where it is
converted into a voltage level corresponding to the amount of
the signal charge, and then output after impedance
conversion in a two stage source follower amplifier.
and the clock noise component are output at the DS pin.
reduced clock noise, etc., by carrying out differential
amplification of the OS and DS outputs externally.
The signal charge transferred to the output region is first sent
The last gate of the CCD transfer region is connected to an
The DC level component not containing the optical signal
It is possible to obtain a signal with a high S/N ratio with
V
DS
1
, ø
2
clock pins, it is possible to reduce the heat
1L
). By driving this pin independent of the
DS
) are the voltage values given in the
MN3672RE
(Preliminary)