lc72136nm Sanyo Semiconductor Corporation, lc72136nm Datasheet - Page 12

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lc72136nm

Manufacturer Part Number
lc72136nm
Description
Pll Frequency Systhesizer
Manufacturer
Sanyo Semiconductor Corporation
Datasheet
Continued from preceding page.
DO Output Data (Serial Data Output) Structure
3. OUT mode
DO Output Data
(11)
(12)
No.
No.
(1)
(2)
(3)
IF counter control data
IFS
LSI test data
TEST 0 to TEST3
I/O port data
I2, I1
PLL unlock data
UL
IF counter binary data
C19 to C0
Control block/data
Control block/data
• This data should be set to 1 in normal operation. Setting this data to 0 switches
• LSI test data
• Data latched from the states of the I/O ports, pins IO1 and IO2.
• Data latched from the state of the unlock detection circuit
• Data latched from the state of the IF counter, which is a 20-bit binary counter.
the LC72136N to a reduced input sensitivity mode in which the sensitivity is reduced by
10 to 30 mVrms.
* See the “IF Counter Operation” item for details.
TEST0
TEST1
TEST2
All the test data is set to 0 following a power-on reset.
This data reflects the pin states, regardless of whether they are in input or output mode.
The data is latched when OUT mode is selected.
I1
I2
UL
UL
C19
C0
IO1 pin state
IO2 pin state
0: Unlocked
1: Locked or in detection stopped mode
Binary counter LSB
Binary counter MSB
All three bits must be set to 0.
High: 1
Low: 0
LC72136N, 72136NM
Description
Description
IOC1,
IOC2
UL0,
UL1
CTE,
GT0,
GT1
Related data
Related data
No. 5608-12/23

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