lc72136 Sanyo Semiconductor Corporation, lc72136 Datasheet - Page 10

• Manufacturer Part Number: lc72136
• Description: Frequency Synthesizer Electronic Tuning
• Manufacturer: Sanyo Semiconductor Corporation

DI Control Data Functions
No.
(1)
(2)
(3)
(4)
(5)
Programmable divider data • Data that sets the programmable divider
P0 to P15
DVS, SNS
Reference divider data
R0 to R3
XS
IF counter control data
CTE
GT0, GT1
I/O port specification data
IOC1, IOC2
Output port data
BO1 to BO5, IO1, IO2
Control block/data
• Selects the signal input pin (AMIN or FMIN) for the programmable divider, switches the
• Reference frequency (fref) selection data
• Oscillator margin selection data
• IF counter measurement start specification
• IF counter measurement time determination
• Data that specifies input or output for the I/O dual-use pins
• BO1 to BO5, IO1, and IO2 output state data
• “Data = 0: Open” is selected following a power-on reset.
A binary value in which P15 is the MSB. The LSB changes depending on DVS and SNS.
Note: P0 to P3 are ignored when P4 is the LSB.
frequency range, and determines the BOF pin output state. (*: Don’t care.)
Note: See the “Programmable Divider” item for details.
Note: PLL INHIBIT
XS = 0: “Reduction mode” The oscillator margin is reduced and the crystal radiation
XS = 1: Normal mode.
Normal mode is selected following a power-on reset.
CTE = 1: Counter start
CTE = 0: Counter reset
Note: See the “IF Counter Structure” item for details.
Data: 0 = input mode, 1 = output mode
Data: 0 = open, 1 = low
DVS
DVS
GT1
R3
1
0
0
1
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
1
1
The programmable divider and IF counter blocks are stopped, the FMIN, AMIN,
and IFIN pins go to the pulled-down state, and the charge pump output pin goes to
the high-impedance state.
is reduced.
SNS
SNS
GT0
R2
*
1
0
*
1
0
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
1
0
1
LSB
Input pin
P0
P0
P4
R1
FMIN
AMIN
AMIN
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
LC72136, 72136M
Measurement time (ms)
Divisor setting (N)
R0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
272 to 65535
272 to 65535
32
64
Description
4
8
4 to 4095
Input frequency range
10 to 160 MHz
0.5 to 10 MHz
2 to 40 MHz
PLL INHIBIT + Xtal OSC STOP
Reference frequency (kHz)
Twice the value of the setting
The value of the setting
The value of the setting
PLL INHIBIT
25
25
25
25
12.5
15
6.25
3.125
3.125
5
5
5
1
3
Wait time (ms)
Actual divisor
3 to 4
3 to 4
7 to 8
7 to 8
BOF pin
Open
Open
Low
Continued on next page.
IFS
IOC1
IOC2
Related data
No. 5038-10/23