lc72131m Sanyo Semiconductor Corporation, lc72131m Datasheet - Page 10

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lc72131m

Manufacturer Part Number
lc72131m
Description
Am/fm Pll Frequency Synthesizer
Manufacturer
Sanyo Semiconductor Corporation
Datasheet

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2. DI Control Data Functions
No.
(1)
(2)
(3)
(4)
(5)
Programmable divider data • Data that sets the divisor of the programmable divider.
P0 to P15
DVS, SNS
Reference divider data
R0 to R3
XS
IF counter control data
CTE
GT0, GT1
I/O port specification data
IOC1, IOC2
Output port data
BO1 to BO4, IO1, IO2
Control block/data
• Selects the signal input pin (AMIN or FMIN) for the programmable divider, switches
• Reference frequency (fref) selection data.
• Crystal resonator selection
• IF counter measurement start data
• Determines the IF counter measurement period.
• Specifies the I/O direction for the bidirectional pins IO1 and IO2.
• Data that determines the output from the BO1 to BO4, IO1 and IO2 output ports
• The data = 0 (open) state is selected after the power-on reset.
A binary value in which P15 is the MSB. The LSB changes depending on
DVS and SNS. (*: don’t care)
Note: P0 to P3 are ignored when P4 is the LSB.
the input frequency range. (*: don’t care)
Note: See the “Programmable Divider Structure” item for more information.
Note: PLL INHIBIT
XS = 0: 4.5 MHz
XS = 1: 7.2 MHz
The 7.2 MHz frequency is selected after the power-on reset.
CTE = 1: Counter start
CTE = 0: Counter reset
Note: See the “IF Counter Structure” item for more information.
Data: 0 = input mode, 1 = output mode
Data: 0 = open, 1 = low
DVS
DVS
GT1
R3
1
0
0
1
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
1
1
The programmable divider block and the IF counter block are stopped, the FMIN,
AMIN, and IFIN pins are set to the pull-down state (ground), and the charge pump
goes to the high impedance state.
SNS
SNS
GT0
R2
*
1
0
*
1
0
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
1
0
1
LSB
P0
P0
P4
R1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
Input pin
LC72131, 72131M
Measurement time (ms)
FMIN
AMIN
AMIN
Divisor setting (N)
R0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
272 to 65535
272 to 65535
32
64
4
8
Functions
4 to 4095
PLL INHIBIT + Xtal OSC STOP
Reference frequency (kHz)
Input frequency range
Twice the value of the setting
The value of the setting
The value of the setting
10 to 160 MHz
0.5 to 10 MHz
PLL INHIBIT
2 to 40 MHz
100
50
25
25
12.5
10
15
6.25
3.125
3.125
9
5
1
3
Wait time (ms)
Actual divisor
3 to 4
3 to 4
7 to 8
7 to 8
Continued on next page.
IFS
IOC1
IOC2
Related data
No. 4921-10/23

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