cxa2067as Sony Electronics, cxa2067as Datasheet
cxa2067as
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cxa2067as Summary of contents
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... Preamplifier for High-Resolution Computer Display Description The CXA2067AS is a bipolar IC developed for high-resolution computer displays. Features • Wide-band amplifier: 170 MHz@–3 dB (Typ) • Input dynamic range: 1.0 Vp-p (typ) • High gain preamplifier (17 dB) • and single package (SDIP 30 pins) • ...
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... LPF CONTRAST GAIN CONTROL DATA BLANKING BRIGHTNESS MODE BLANKING BUFFER AMP BLANKING PULSE OSD PULSE (13PIN) OSD SW YS PULSE (17PIN) SYNC SEPARATOR SVSW Same as R channel Same as R channel —2— CXA2067AS 30 CSYNC/VDET 12V 28 S/H-R 27 ROUT 26 GND-R 25 S/H-G 24 GOUT ...
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... 14k 300 —3— CXA2067AS Description I C bus standard SDA 2 (serial data) input/output. VILMAX=1.5 V VIHMIN=3.5 V VOLMAX=0 bus standard SCL (serial clock) input/output. VILMAX=1.5 V VIHMIN=3.5 V DAC output for cut-off adjustment. Output ...
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... 10k 10k 17 —4— CXA2067AS Description Sync-on-green signal input. Input via a capacitor. Clamp pulse (positive polarity) input. VILMAX=0.8 V VIHMIN=2.8 V OSD control inputs. VILMAX=0.8 V VIHMIN=2 power supply. (B channel) YS (OSD BLK) control input. VILMAX=0.8 V VIHMIN=2.8 V ...
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... 300 —5— CXA2067AS Description Blanking pulse input. Set the V blanking pulse width to 300 µs or more. VILMAX=0.8 V VIHMIN=2.8 V Ground and B outputs. Brightness sample-and-hold. Connect to GND via a capacitor power supply. (G channel power supply. (R channel) ...
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... Pin Pin Symbol No. voltage CSYNC 30 — /VDET Equivalent circuit 100 5k 20k 30 500 —6— CXA2067AS Description Sync-on-green signal sync separator output/video detector output. Either of them is selected by SVSW bus. Typ. : High=4.3 V Low=0.2 V (positive polarity) ...
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... Performs the Pin 4 (COF G) output voltage control Output voltage minimum (1 V) 255 : Output voltage maximum (4 V) Performs the Pin 5 (COF B) output voltage control Output voltage minimum (1 V) 255 : Output voltage maximum (4 V) —7— CXA2067AS BIT2 BIT1 BIT0 OSD GAIN VSOFF Note) : don’t care ...
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... Gain maximum (+17 dB) Performs the Pin 30 output control Output Output OFF Switches the Pin 30 output signal (sync separator/video detector Sync separator output 1 : Video detector output Performs the control of VBLK sync DAC refresh function Function operation Function operation OFF —8— CXA2067AS ...
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... STA 4.7 — DAT 0 — DAT 250 — — — — — STO 4.7 — SU —9— CXA2067AS Max. Unit 5.0 V 1.5 V 0.4 V 400 kHz — µs — µs — µs — µs — µs — ns — µs 300 ns — ...
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... Measure the output signal amplitude Vout level when a 0.7 Vp-p video signal is input. GCONT1 : Contrast=SubContrast=FF GCONT2 : Contrast=00/SubContrast=FF Input signal 0.7Vp-p Measure the output signal amplitude Vout level when a 0.7 Vp-p video signal is input. Contrast=FF/SubContrast=00 Input signal 0.7Vp-p —10— CXA2067AS Min. Typ. Max. Unit 85 115 140 mA 29.5 45 55.5 ...
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... Measure the BLK level of the output signal when the BLK pulse is input. BLK level (VBLK1) BLK level (VBLK2) GND Vth=50% Rise Delay Fall Delay Vth=50% Vth=50% 0.7Vp-p Rise Fall Delay Delay Vth=50% —11— CXA2067AS Min. Typ. Max. Unit 4.5 5 — Vp-p — 0 150 mVp-p 0.4 0 2.2 2.6 3 — ...
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... VDET amplitude Measurement contents Measure the DAC output voltage (Pin 6) for COFF=00/FF. Input the crosshatch signal of DotClock=100 MHz/0.7 Vp-p and measure the VDET output amplitude. SW SW=1/VDET LEVEL=0 Input signal 0.7Vp-p 10ns 10ns —12— CXA2067AS Min. Typ. Max. Unit — 1 1.3 V 3.9 4 — 3.85 4 — ...
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... RIN GOUT 8 V GND GIN SYNC IN S/H BIN BOUT CLP GND-B 13 OSD-R BLKING 18 14 OSD OSD —13— CXA2067AS 47 F 12V 0.1 F 0.1 F Rch Output 0.1 F Gch Output 47 F 12V 0.1 F 0.1 F Bch Output 47 F 12V 0.1 F ...
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... RIN GOUT 8 V GND GIN SYNC IN S/H BIN BOUT CLP GND-B 13 OSD-R BLKING 18 14 OSD OSD —14— CXA2067AS 47 F 12V 0.1 F 0.1 F Rch Output 0.1 F Gch Output 47 F 12V 0.1 F 0.1 F Bch Output 47 F 12V 0.1 F ...
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... CXA2067AS ...
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... GOUT GND GIN SYNC IN S/H BIN BOUT 20 12 CLP GND OSD-R BLKING 14 OSD OSD —16— CXA2067AS 47 F 12V 0.1 F 0.1 F Rch Output 0.1 F Gch Output 47 F 12V 0.1 F 0.1 F Bch Output YS input 47 F 12V 0.1 F ...
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... The signals to RIN, GIN and BIN should be input via a clamp capacitor with the low impedance. 6. Set the output OFF when the VDET/CSYNC output is not used. (The cross talk may deteriorate) and V R/G/B, the ceramic capacitor and the electrolysis capacitor CC CC —17— CXA2067AS ...
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... SDIP (PLASTIC 1.778 0.5 ± 0.1 0.9 ± 0.15 PACKAGE STRUCTURE MOLDING COMPOUND LEAD TREATMENT LEAD MATERIAL PACKAGE MASS —18— CXA2067AS 0° to 15° Two kinds of package surface: 1.All mat surface type. 2.All mirror surface type. EPOXY RESIN SOLDER/PALLADIUM PLATING COPPER ALLOY 1.8g ...